Searched refs:Pixel (Results 1 – 25 of 84) sorted by relevance
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| /linux/Documentation/devicetree/bindings/arm/ |
| A D | google.yaml | 13 ARM platforms using SoCs designed by Google branded "Tensor" used in Pixel
16 Currently upstream this is devices using "gs101" SoC which is found in Pixel
17 6, Pixel 6 Pro and Pixel 6a.
26 - Marketing name ("Pixel 6")
37 - description: Google Pixel 6 / Oriole
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| /linux/Documentation/devicetree/bindings/display/bridge/ |
| A D | fsl,imx8qxp-pxl2dpi.yaml | 7 title: Freescale i.MX8qxp Pixel Link to Display Pixel Interface
13 The Freescale i.MX8qxp Pixel Link to Display Pixel Interface(PXL2DPI)
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| A D | fsl,imx8qxp-pixel-link.yaml | 7 title: Freescale i.MX8qm/qxp Display Pixel Link
13 The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
21 The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU)
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| A D | fsl,imx8qxp-pixel-combiner.yaml | 7 title: Freescale i.MX8qm/qxp Pixel Combiner
13 The Freescale i.MX8qm/qxp Pixel Combiner takes two output streams from a
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| /linux/Documentation/devicetree/bindings/display/rockchip/ |
| A D | rockchip-vop2.yaml | 51 - description: Pixel clock for video port 0.
52 - description: Pixel clock for video port 1.
53 - description: Pixel clock for video port 2.
54 - description: Pixel clock for video port 3.
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| /linux/drivers/media/platform/st/stm32/ |
| A D | Kconfig | 20 tristate "STM32 Digital Camera Memory Interface Pixel Processor (DCMIPP) support"
30 Pixel Processor (DCMIPP) available as a v4l2 device.
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| /linux/Documentation/devicetree/bindings/clock/ |
| A D | qcom,gcc-msm8953.yaml | 28 - description: Pixel clock from DSI PHY0
30 - description: Pixel clock from DSI PHY1
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| A D | qcom,gcc-msm8976.yaml | 29 - description: Pixel clock from DSI PHY0
31 - description: Pixel clock from DSI PHY1
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| A D | qcom,sm7150-dispcc.yaml | 31 - description: Pixel clock from MDSS DSI PHY0
33 - description: Pixel clock from MDSS DSI PHY1
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| A D | qcom,sdm845-dispcc.yaml | 31 - description: Pixel clock from DSI PHY0
33 - description: Pixel clock from DSI PHY1
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| A D | qcom,dispcc-sm6125.yaml | 27 - description: Pixel clock from DSI PHY0
28 - description: Pixel clock from DSI PHY1
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| A D | qcom,sm8450-dispcc.yaml | 31 - description: Pixel clock from DSI PHY0
33 - description: Pixel clock from DSI PHY1
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| A D | qcom,sm8550-dispcc.yaml | 36 - description: Pixel clock from DSI PHY0
38 - description: Pixel clock from DSI PHY1
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| A D | qcom,dispcc-sm8x50.yaml | 34 - description: Pixel clock from DSI PHY0
36 - description: Pixel clock from DSI PHY1
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| A D | qcom,sm6375-dispcc.yaml | 30 - description: Pixel clock from DSI PHY
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| A D | qcom,sm6115-dispcc.yaml | 28 - description: Pixel clock from DSI PHY0
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| A D | qcom,sm4450-dispcc.yaml | 33 - description: Pixel clock from DSI PHY0
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| /linux/Documentation/devicetree/bindings/gpu/ |
| A D | arm,mali-utgard.yaml | 74 - pp # Pixel Processor broadcast interrupt (mali-450 only)
75 - pp0 # Pixel Processor X interrupt (X from 0 to 7)
76 - ppmmu0 # Pixel Processor X MMU interrupt (X from 0 to 7)
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| /linux/Documentation/devicetree/bindings/media/ |
| A D | fsl,imx6ull-pxp.yaml | 8 title: Freescale Pixel Pipeline
15 The Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine
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| A D | nxp,imx8-isi.yaml | 15 sources. The inputs to the ISI go through Pixel Link interfaces, and their
59 Ports represent the Pixel Link inputs to the ISI. Their number and
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| A D | st,stm32-dcmipp.yaml | 7 title: STMicroelectronics STM32 DCMIPP Digital Camera Memory Interface Pixel Processor
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| /linux/Documentation/gpu/amdgpu/display/ |
| A D | dc-glossary.rst | 31 Bits Per Pixel
34 * PCLK: Pixel Clock
41 * PPLL: Pixel PLL
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| /linux/drivers/video/fbdev/ |
| A D | pxa3xx-regs.h | 91 #define LCCR1_DisWdth(Pixel) (((Pixel) - 1) << FShft (LCCR1_PPL)) argument
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| /linux/drivers/media/platform/nxp/ |
| A D | Kconfig | 47 tristate "NXP i.MX Pixel Pipeline (PXP)"
53 The i.MX Pixel Pipeline is a memory-to-memory engine for scaling,
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| /linux/Documentation/devicetree/bindings/display/panel/ |
| A D | lg,sw43408.yaml | 13 This panel is used on the Pixel 3, it is a 60hz OLED panel which
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