Searched refs:QSPI (Results 1 – 25 of 41) sorted by relevance
12
153 label = "QSPI.SPL";157 label = "QSPI.SPL.backup1";161 label = "QSPI.SPL.backup2";165 label = "QSPI.SPL.backup3";169 label = "QSPI.u-boot";173 label = "QSPI.u-boot-spl-os";177 label = "QSPI.u-boot-env";181 label = "QSPI.u-boot-env.backup1";185 label = "QSPI.kernel";189 label = "QSPI.file-system";
492 label = "QSPI.SPL";496 label = "QSPI.SPL.backup1";500 label = "QSPI.SPL.backup2";504 label = "QSPI.SPL.backup3";508 label = "QSPI.u-boot";512 label = "QSPI.u-boot-spl-os";516 label = "QSPI.u-boot-env";520 label = "QSPI.u-boot-env.backup1";524 label = "QSPI.kernel";528 label = "QSPI.file-system";
544 label = "QSPI.SPL";548 label = "QSPI.u-boot";552 label = "QSPI.u-boot-spl-os";556 label = "QSPI.u-boot-env";560 label = "QSPI.u-boot-env.backup1";564 label = "QSPI.kernel";568 label = "QSPI.file-system";
454 label = "QSPI.U_BOOT";458 label = "QSPI.U_BOOT.backup";462 label = "QSPI.U-BOOT-SPL_OS";466 label = "QSPI.U_BOOT_ENV";470 label = "QSPI.U-BOOT-ENV.backup";474 label = "QSPI.KERNEL";478 label = "QSPI.FILESYSTEM";
750 status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */899 status = "disabled"; /* Disable GPMC (NAND) when enabling QSPI */921 label = "QSPI.U_BOOT";925 label = "QSPI.U_BOOT.backup";929 label = "QSPI.U-BOOT-SPL_OS";933 label = "QSPI.U_BOOT_ENV";937 label = "QSPI.U-BOOT-ENV.backup";941 label = "QSPI.KERNEL";945 label = "QSPI.FILESYSTEM";
765 label = "QSPI.U_BOOT";769 label = "QSPI.U_BOOT.backup";773 label = "QSPI.U-BOOT-SPL_OS";777 label = "QSPI.U_BOOT_ENV";781 label = "QSPI.U-BOOT-ENV.backup";785 label = "QSPI.KERNEL";789 label = "QSPI.FILESYSTEM";
7 title: Qualcomm Quad Serial Peripheral Interface (QSPI)12 description: The QSPI controller allows SPI protocol communication in single,46 - description: QSPI core clock
7 title: TI QSPI controller48 Name of the hwmod associated to the QSPI. This is for legacy55 Handle to system control region containing QSPI chipselect register
7 title: Xilinx Zynq QSPI controller10 The Xilinx Zynq QSPI controller is used to access multi-bit serial flash
18 QSPI to corresponding slave device.27 QSPI to corresponding slave device.
10 SPI and QSPI controllers on Microchip PolarFire SoC and the "soft"/24 - const: microchip,coreqspi-rtl-v2 # FPGA QSPI
127 Flag to indicate that QSPI return clock is used to latch the read128 data rather than the QSPI clock. Make sure that QSPI return clock
7 title: Peripheral-specific properties for the Cadence QSPI controller.
7 title: STMicroelectronics STM32 Quad Serial Peripheral Interface (QSPI)
343 label = "QSPI.u-boot";347 label = "QSPI.u-boot-env";351 label = "QSPI.skern";355 label = "QSPI.pmmc-firmware";359 label = "QSPI.kernel";363 label = "QSPI.u-boot-spl-os";367 label = "QSPI.file-system";
410 label = "QSPI.u-boot-spl-os";414 label = "QSPI.u-boot-env";418 label = "QSPI.skern";422 label = "QSPI.pmmc-firmware";426 label = "QSPI.kernel";430 label = "QSPI.file-system";
32 The SPI flash connected to the system controller's QSPI controller.35 for Auto Update. The MSS and system controller have separate QSPI
294 tristate "Freescale Coldfire QSPI controller"403 tristate "Freescale QSPI controller"673 tristate "Microchip FPGA QSPI controllers"676 This enables the QSPI driver for Microchip FPGA QSPI controllers.782 tristate "DRA7xxx QSPI controller support"883 tristate "Renesas RSPI/QSPI controller"896 tristate "QTI QSPI controller"899 QSPI(Quad SPI) driver for Qualcomm QSPI controller.1080 tristate "NVIDIA Tegra QSPI Controller"1084 QSPI driver for NVIDIA Tegra QSPI Controller interface. This[all …]
20 - QSPI
14 - Dual mode QSPI
338 QSPI, enumerator430 INTC_VECT(QSPI, 0xE60),438 INTC_GROUP(SPI, HSPI, RSPI, QSPI),
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