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Searched refs:REG_CLR_FLD (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/accel/ivpu/
A Divpu_hw_ip.c238 val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN, EN, val); in idle_gen_drive_37xx()
250 val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val); in idle_gen_drive_40xx()
416 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, TOP_NOC, val); in host_ss_clk_drive_37xx()
433 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, TOP_NOC, val); in host_ss_clk_drive_40xx()
434 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, DSS_MAS, val); in host_ss_clk_drive_40xx()
435 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, CSS_MAS, val); in host_ss_clk_drive_40xx()
480 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, TOP_NOC, val); in host_ss_rst_drive_40xx()
481 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, DSS_MAS, val); in host_ss_rst_drive_40xx()
482 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, CSS_MAS, val); in host_ss_rst_drive_40xx()
558 val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val); in top_noc_qreqn_drive_40xx()
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A Divpu_hw_btrs.c388 val = REG_CLR_FLD(VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL, I3, val); in d0i3_drive_mtl()
413 val = REG_CLR_FLD(VPU_HW_BTRS_LNL_D0I3_CONTROL, I3, val); in d0i3_drive_lnl()
542 val = REG_CLR_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, PERF_CLK, val); in ivpu_hw_btrs_profiling_freq_reg_set_lnl()
A Divpu_hw_reg_io.h39 #define REG_CLR_FLD(REG, FLD, val) \ macro

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