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Searched refs:REG_GET (Results 1 – 25 of 126) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/
A Ddcn35_hubbub.c53 REG_GET(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, in dcn35_init_crb()
56 REG_GET(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, in dcn35_init_crb()
59 REG_GET(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, in dcn35_init_crb()
62 REG_GET(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, in dcn35_init_crb()
409 REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, in hubbub35_wm_read_state()
415 REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, in hubbub35_wm_read_state()
434 REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, in hubbub35_wm_read_state()
440 REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, in hubbub35_wm_read_state()
460 REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, in hubbub35_wm_read_state()
466 REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, in hubbub35_wm_read_state()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn20/
A Ddcn20_hubp.c1124 REG_GET(HUBPRET_CONTROL, in hubp2_read_state_common()
1143 REG_GET(BLANK_OFFSET_1, in hubp2_read_state_common()
1146 REG_GET(DST_DIMENSIONS, in hubp2_read_state_common()
1184 REG_GET(NOM_PARAMETERS_4, in hubp2_read_state_common()
1187 REG_GET(NOM_PARAMETERS_5, in hubp2_read_state_common()
1219 REG_GET(NOM_PARAMETERS_6, in hubp2_read_state_common()
1222 REG_GET(NOM_PARAMETERS_7, in hubp2_read_state_common()
1284 REG_GET(HUBP_CLK_CNTL, in hubp2_read_state_common()
1357 REG_GET(HUBPRET_CONTROL, in hubp2_validate_dml_output()
1453 REG_GET(BLANK_OFFSET_1, in hubp2_validate_dml_output()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/pg/dcn35/
A Ddcn35_pg_cntl.c57 REG_GET(DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); in pg_cntl35_dsc_pg_status()
60 REG_GET(DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); in pg_cntl35_dsc_pg_status()
63 REG_GET(DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); in pg_cntl35_dsc_pg_status()
66 REG_GET(DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); in pg_cntl35_dsc_pg_status()
103 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); in pg_cntl35_dsc_pg_control()
163 REG_GET(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); in pg_cntl35_hubp_dpp_pg_status()
208 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); in pg_cntl35_hubp_dpp_pg_control()
252 REG_GET(DOMAIN25_PG_STATUS, in pg_cntl35_hpo_pg_status()
300 REG_GET(DOMAIN22_PG_STATUS, in pg_cntl35_io_clk_status()
350 REG_GET(DOMAIN24_PG_STATUS, in pg_cntl35_plane_otg_status()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn10/
A Ddcn10_hubp.c95 REG_GET(DCHUBP_CNTL, in hubp1_get_underflow_status()
879 REG_GET(HUBPRET_CONTROL, in hubp1_read_state_common()
908 REG_GET(BLANK_OFFSET_1, in hubp1_read_state_common()
911 REG_GET(DST_DIMENSIONS, in hubp1_read_state_common()
942 REG_GET(NOM_PARAMETERS_0, in hubp1_read_state_common()
946 REG_GET(NOM_PARAMETERS_1, in hubp1_read_state_common()
949 REG_GET(NOM_PARAMETERS_4, in hubp1_read_state_common()
952 REG_GET(NOM_PARAMETERS_5, in hubp1_read_state_common()
984 REG_GET(NOM_PARAMETERS_6, in hubp1_read_state_common()
987 REG_GET(NOM_PARAMETERS_7, in hubp1_read_state_common()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn401/
A Ddcn401_hubp.c768 REG_GET(HUBPRET_CONTROL, in hubp401_read_state()
801 REG_GET(BLANK_OFFSET_1, in hubp401_read_state()
804 REG_GET(DST_DIMENSIONS, in hubp401_read_state()
829 REG_GET(NOM_PARAMETERS_0, in hubp401_read_state()
832 REG_GET(NOM_PARAMETERS_1, in hubp401_read_state()
835 REG_GET(NOM_PARAMETERS_4, in hubp401_read_state()
838 REG_GET(NOM_PARAMETERS_5, in hubp401_read_state()
858 REG_GET(NOM_PARAMETERS_2, in hubp401_read_state()
861 REG_GET(NOM_PARAMETERS_3, in hubp401_read_state()
864 REG_GET(NOM_PARAMETERS_6, in hubp401_read_state()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn301/
A Ddcn301_panel_cntl.c57 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period); in dcn301_get_16_bit_backlight_from_pwm()
58 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count); in dcn301_get_16_bit_backlight_from_pwm()
60 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &bl_pwm); in dcn301_get_16_bit_backlight_from_pwm()
61 REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en); in dcn301_get_16_bit_backlight_from_pwm()
106 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value); in dcn301_panel_cntl_hw_init()
134 REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV, in dcn301_panel_cntl_hw_init()
163 REG_GET(PWRSEQ_CNTL, PANEL_BLON, &value); in dcn301_is_panel_backlight_on()
173 REG_GET(PWRSEQ_STATE, PANEL_PWRSEQ_TARGET_STATE_R, &pwr_seq_state); in dcn301_is_panel_powered_on()
191 REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV, in dcn301_store_backlight_level()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn21/
A Ddcn21_hubp.c90 REG_GET(VBLANK_PARAMETERS_5, in apply_DEDCN21_142_wa_for_hostvm_deadline()
98 REG_GET(VBLANK_PARAMETERS_6, in apply_DEDCN21_142_wa_for_hostvm_deadline()
106 REG_GET(FLIP_PARAMETERS_3, in apply_DEDCN21_142_wa_for_hostvm_deadline()
114 REG_GET(FLIP_PARAMETERS_4, in apply_DEDCN21_142_wa_for_hostvm_deadline()
267 REG_GET(HUBPRET_CONTROL, in hubp21_validate_dml_output()
360 REG_GET(BLANK_OFFSET_1, in hubp21_validate_dml_output()
362 REG_GET(DST_DIMENSIONS, in hubp21_validate_dml_output()
401 REG_GET(NOM_PARAMETERS_4, in hubp21_validate_dml_output()
403 REG_GET(NOM_PARAMETERS_5, in hubp21_validate_dml_output()
419 REG_GET(NOM_PARAMETERS_6, in hubp21_validate_dml_output()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_panel_cntl.c58 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period); in dce_get_16_bit_backlight_from_pwm()
59 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count); in dce_get_16_bit_backlight_from_pwm()
62 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm)); in dce_get_16_bit_backlight_from_pwm()
63 REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en); in dce_get_16_bit_backlight_from_pwm()
99 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value); in dce_panel_cntl_hw_init()
119 REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV, in dce_panel_cntl_hw_init()
153 REG_GET(PWRSEQ_CNTL, LVTMA_PWRSEQ_TARGET_STATE, &pwrseq_target_state); in dce_is_panel_backlight_on()
166 REG_GET(PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &pwr_seq_state); in dce_is_panel_powered_on()
184 REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV, in dce_store_backlight_level()
/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn10/
A Ddcn10_mpc.c152 REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel); in mpc1_is_mpcc_idle()
153 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); in mpc1_is_mpcc_idle()
154 REG_GET(MPCC_STATUS[mpcc_id], MPCC_IDLE, &idle); in mpc1_is_mpcc_idle()
166 REG_GET(MPCC_TOP_SEL[mpcc_id], in mpc1_assert_mpcc_idle_before_connect()
398 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); in mpc1_mpc_init_single_inst()
425 REG_GET(MUX[tree->opp_id], MPC_OUT_MUX, &out_mux); in mpc1_init_mpcc_list_from_hw()
429 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); in mpc1_init_mpcc_list_from_hw()
430 REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel); in mpc1_init_mpcc_list_from_hw()
431 REG_GET(MPCC_BOT_SEL[mpcc_id], MPCC_BOT_SEL, &bot_sel); in mpc1_init_mpcc_list_from_hw()
465 REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id); in mpc1_read_mpcc_state()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/
A Ddcn32_hubbub.c54 REG_GET(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, in dcn32_init_crb()
57 REG_GET(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, in dcn32_init_crb()
60 REG_GET(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, in dcn32_init_crb()
63 REG_GET(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, in dcn32_init_crb()
66 REG_GET(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT, in dcn32_init_crb()
858 REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, in hubbub32_wm_read_state()
864 REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, in hubbub32_wm_read_state()
878 REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, in hubbub32_wm_read_state()
884 REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, in hubbub32_wm_read_state()
898 REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, in hubbub32_wm_read_state()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn10/
A Ddcn10_optc.c758 REG_GET(OTG_V_SYNC_A_CNTL, in optc1_enable_reset_trigger()
1298 REG_GET(OTG_STEREO_STATUS, in optc1_is_stereo_left_eye()
1335 REG_GET(OTG_CONTROL, in optc1_read_otg_state()
1342 REG_GET(OTG_V_SYNC_A_CNTL, in optc1_read_otg_state()
1345 REG_GET(OTG_V_TOTAL, in optc1_read_otg_state()
1348 REG_GET(OTG_V_TOTAL_MAX, in optc1_read_otg_state()
1351 REG_GET(OTG_V_TOTAL_MIN, in optc1_read_otg_state()
1372 REG_GET(OTG_H_SYNC_A_CNTL, in optc1_read_otg_state()
1375 REG_GET(OTG_H_TOTAL, in optc1_read_otg_state()
1409 REG_GET(OTG_CONTROL, in optc1_get_otg_active_size()
[all …]
/linux/drivers/gpu/drm/amd/display/dmub/src/
A Ddmub_dcn31.c68 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp); in dmub_dcn31_get_fb_base_offset()
71 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp); in dmub_dcn31_get_fb_base_offset()
89 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset); in dmub_dcn31_reset()
119 REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &pwait_mode); in dmub_dcn31_reset()
292 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enable); in dmub_dcn31_is_hw_init()
301 REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported); in dmub_dcn31_is_supported()
456 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); in dmub_dcn31_get_diagnostic_data()
459 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset); in dmub_dcn31_get_diagnostic_data()
462 REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset); in dmub_dcn31_get_diagnostic_data()
465 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); in dmub_dcn31_get_diagnostic_data()
[all …]
A Ddmub_dcn401.c48 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp); in dmub_dcn401_get_fb_base_offset()
51 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp); in dmub_dcn401_get_fb_base_offset()
69 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset); in dmub_dcn401_reset()
304 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init); in dmub_dcn401_is_hw_init()
313 REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported); in dmub_dcn401_is_supported()
451 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); in dmub_dcn401_get_diagnostic_data()
454 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset); in dmub_dcn401_get_diagnostic_data()
457 REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset); in dmub_dcn401_get_diagnostic_data()
460 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); in dmub_dcn401_get_diagnostic_data()
532 REG_GET(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_STAT, &status); in dmub_dcn401_read_reg_inbox0_rsp_int_status()
[all …]
A Ddmub_dcn35.c73 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp); in dmub_dcn35_get_fb_base_offset()
76 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp); in dmub_dcn35_get_fb_base_offset()
94 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset); in dmub_dcn35_reset()
124 REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &pwait_mode); in dmub_dcn35_reset()
133 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enabled); in dmub_dcn35_reset()
343 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enable); in dmub_dcn35_is_hw_init()
352 REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported); in dmub_dcn35_is_supported()
510 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); in dmub_dcn35_get_diagnostic_data()
513 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset); in dmub_dcn35_get_diagnostic_data()
516 REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset); in dmub_dcn35_get_diagnostic_data()
[all …]
A Ddmub_dcn20.c72 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp); in dmub_dcn20_get_fb_base_offset()
75 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp); in dmub_dcn20_get_fb_base_offset()
100 REG_GET(DMCUB_CNTL, DMCUB_SOFT_RESET, &in_reset); in dmub_dcn20_reset()
353 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init); in dmub_dcn20_is_hw_init()
362 REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported); in dmub_dcn20_is_supported()
458 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); in dmub_dcn20_get_diagnostic_data()
461 REG_GET(DMCUB_CNTL, DMCUB_SOFT_RESET, &is_soft_reset); in dmub_dcn20_get_diagnostic_data()
464 REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset); in dmub_dcn20_get_diagnostic_data()
467 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); in dmub_dcn20_get_diagnostic_data()
470 REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled); in dmub_dcn20_get_diagnostic_data()
[all …]
A Ddmub_dcn32.c74 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp); in dmub_dcn32_get_fb_base_offset()
77 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp); in dmub_dcn32_get_fb_base_offset()
95 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset); in dmub_dcn32_reset()
321 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init); in dmub_dcn32_is_hw_init()
330 REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported); in dmub_dcn32_is_supported()
466 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); in dmub_dcn32_get_diagnostic_data()
469 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset); in dmub_dcn32_get_diagnostic_data()
472 REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset); in dmub_dcn32_get_diagnostic_data()
475 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); in dmub_dcn32_get_diagnostic_data()
478 REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled); in dmub_dcn32_get_diagnostic_data()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hpo/dcn31/
A Ddcn31_hpo_dp_stream_encoder.c497 REG_GET(DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL, in dcn31_hpo_dp_stream_enc_update_dp_info_packets()
539 REG_GET(DP_SYM32_ENC_SDP_GSP_CONTROL0, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, &gsp0_enabled); in hpo_dp_is_gsp_enabled()
540 REG_GET(DP_SYM32_ENC_SDP_GSP_CONTROL2, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, &gsp2_enabled); in hpo_dp_is_gsp_enabled()
694 REG_GET(DP_SYM32_ENC_CONTROL, in dcn31_hpo_dp_stream_enc_read_state()
696 REG_GET(DP_SYM32_ENC_VID_STREAM_CONTROL, in dcn31_hpo_dp_stream_enc_read_state()
698 REG_GET(DP_STREAM_ENC_INPUT_MUX_CONTROL, in dcn31_hpo_dp_stream_enc_read_state()
706 REG_GET(DP_SYM32_ENC_SDP_CONTROL, in dcn31_hpo_dp_stream_enc_read_state()
711 REG_GET(DP_STREAM_MAPPER_CONTROL0, in dcn31_hpo_dp_stream_enc_read_state()
715 REG_GET(DP_STREAM_MAPPER_CONTROL1, in dcn31_hpo_dp_stream_enc_read_state()
719 REG_GET(DP_STREAM_MAPPER_CONTROL2, in dcn31_hpo_dp_stream_enc_read_state()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/
A Ddcn21_hubbub.c628 REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, in hubbub21_wm_read_state()
631 REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, in hubbub21_wm_read_state()
634 REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, in hubbub21_wm_read_state()
642 REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, in hubbub21_wm_read_state()
645 REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, in hubbub21_wm_read_state()
648 REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, in hubbub21_wm_read_state()
656 REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, in hubbub21_wm_read_state()
659 REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, in hubbub21_wm_read_state()
662 REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, in hubbub21_wm_read_state()
670 REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, in hubbub21_wm_read_state()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn20/
A Ddcn20_optc.c157 REG_GET(OPTC_DATA_FORMAT_CONTROL, in optc2_get_dsc_status()
281 REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &slave_h_total); in optc2_align_vblanks()
291 REG_GET(OTG_MASTER_UPDATE_LOCK, in optc2_align_vblanks()
297 REG_GET(OTG_V_BLANK_START_END, in optc2_align_vblanks()
299 REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &master_h_total); in optc2_align_vblanks()
420 REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START, &v_blank_start); in optc2_lock_doublebuffer_enable()
422 REG_GET(OTG_H_BLANK_START_END, OTG_H_BLANK_START, &h_blank_start); in optc2_lock_doublebuffer_enable()
502 REG_GET(OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, refresh_rate); in optc2_get_last_used_drr_vtotal()
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn20/
A Ddcn20_stream_encoder.c356 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); in enc2_read_state()
358 REG_GET(DP_DSC_CNTL, DP_DSC_SLICE_WIDTH, &s->dsc_slice_width); in enc2_read_state()
359 REG_GET(DP_SEC_CNTL6, DP_SEC_GSP7_LINE_NUM, &s->sec_gsp_pps_line_num); in enc2_read_state()
361 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference); in enc2_read_state()
362 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num); in enc2_read_state()
364 REG_GET(DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, &s->sec_gsp_pps_enable); in enc2_read_state()
365 REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); in enc2_read_state()
452 REG_GET(DP_SEC_METADATA_TRANSMISSION, in enc2_stream_encoder_update_dp_info_packets()
587 REG_GET(DIG_FIFO_STATUS, in enc2_get_fifo_cal_average_level()
/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn401/
A Ddcn401_dsc.c124 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en); in dsc401_read_state()
125 REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width); in dsc401_read_state()
126 REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bits_per_pixel); in dsc401_read_state()
127 REG_GET(DSCC_PPS_CONFIG3, SLICE_HEIGHT, &s->dsc_slice_height); in dsc401_read_state()
128 REG_GET(DSCC_PPS_CONFIG1, CHUNK_SIZE, &s->dsc_chunk_size); in dsc401_read_state()
129 REG_GET(DSCC_PPS_CONFIG2, PIC_WIDTH, &s->dsc_pic_width); in dsc401_read_state()
130 REG_GET(DSCC_PPS_CONFIG2, PIC_HEIGHT, &s->dsc_pic_height); in dsc401_read_state()
131 REG_GET(DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, &s->dsc_slice_bpg_offset); in dsc401_read_state()
172 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); in dsc401_enable()
195 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); in dsc401_disable()
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn314/
A Ddcn314_dio_stream_encoder.c59 REG_GET(DIG_FE_CNTL, DIG_SYMCLK_FE_ON, &is_symclk_on); in enc314_reset_fifo()
401 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); in enc314_read_state()
403 REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, &s->sec_gsp_pps_line_num); in enc314_read_state()
405 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference); in enc314_read_state()
406 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num); in enc314_read_state()
408 REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, &s->sec_gsp_pps_enable); in enc314_read_state()
409 REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); in enc314_read_state()
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn32/
A Ddcn32_dio_stream_encoder.c372 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); in enc32_read_state()
374 REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, &s->sec_gsp_pps_line_num); in enc32_read_state()
376 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference); in enc32_read_state()
377 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num); in enc32_read_state()
379 REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, &s->sec_gsp_pps_enable); in enc32_read_state()
380 REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); in enc32_read_state()
401 REG_GET(DIG_FE_CNTL, DIG_SYMCLK_FE_ON, &is_symclk_on); in enc32_reset_fifo()
/linux/drivers/gpu/drm/amd/display/dc/gpio/
A Dhw_gpio.c45 REG_GET(MASK_reg, MASK, &gpio->store.mask); in store_registers()
46 REG_GET(A_reg, A, &gpio->store.a); in store_registers()
47 REG_GET(EN_reg, EN, &gpio->store.en); in store_registers()
86 REG_GET(Y_reg, Y, value); in dal_hw_gpio_get_value()
/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn30/
A Ddcn30_mpc.c84 REG_GET(DWB_MUX[dwb_id], MPC_DWB0_MUX_STATUS, &status); in mpc3_is_dwb_idle()
919 REG_GET(RMU_3DLUT_MODE[rmu_idx], in get3dlut_config()
922 REG_GET(RMU_3DLUT_READ_WRITE_CONTROL[rmu_idx], in get3dlut_config()
1476 REG_GET(SHAPER_CONTROL[0], in mpc3_read_mpcc_state()
1478 REG_GET(RMU_3DLUT_MODE[0], in mpc3_read_mpcc_state()
1480 REG_GET(RMU_3DLUT_READ_WRITE_CONTROL[0], in mpc3_read_mpcc_state()
1482 REG_GET(RMU_3DLUT_MODE[0], in mpc3_read_mpcc_state()
1485 REG_GET(SHAPER_CONTROL[1], in mpc3_read_mpcc_state()
1487 REG_GET(RMU_3DLUT_MODE[1], in mpc3_read_mpcc_state()
1489 REG_GET(RMU_3DLUT_READ_WRITE_CONTROL[1], in mpc3_read_mpcc_state()
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