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Searched refs:REG_GET_FIELD (Results 1 – 25 of 98) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdkfd/
A Dkfd_int_process_v10.c216 encoding = REG_GET_FIELD(context_id1, in event_interrupt_wq_v10()
222 REG_GET_FIELD(context_id1, SQ_INTERRUPT_WORD_AUTO_CTXID1, in event_interrupt_wq_v10()
224 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, in event_interrupt_wq_v10()
226 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, in event_interrupt_wq_v10()
228 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, in event_interrupt_wq_v10()
230 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, in event_interrupt_wq_v10()
232 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, in event_interrupt_wq_v10()
237 REG_GET_FIELD(context_id1, SQ_INTERRUPT_WORD_WAVE_CTXID1, in event_interrupt_wq_v10()
239 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0, in event_interrupt_wq_v10()
241 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0, in event_interrupt_wq_v10()
[all …]
A Dkfd_int_process_v11.c156 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, WLT), in print_sq_intr_info_auto()
170 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0, DATA), in print_sq_intr_info_inst()
171 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0, SH_ID), in print_sq_intr_info_inst()
172 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0, PRIV), in print_sq_intr_info_inst()
173 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0, WAVE_ID), in print_sq_intr_info_inst()
183 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID0, TYPE), in print_sq_intr_info_error()
184 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID0, SH_ID), in print_sq_intr_info_error()
185 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID0, PRIV), in print_sq_intr_info_error()
352 sq_int_enc = REG_GET_FIELD(context_id1, in event_interrupt_wq_v11()
360 sq_int_priv = REG_GET_FIELD(context_id0, in event_interrupt_wq_v11()
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A Dkfd_int_process_v9.c382 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, SE_ID), in event_interrupt_wq_v9()
384 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, WLT), in event_interrupt_wq_v9()
395 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SE_ID), in event_interrupt_wq_v9()
396 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, DATA), in event_interrupt_wq_v9()
397 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SH_ID), in event_interrupt_wq_v9()
398 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, PRIV), in event_interrupt_wq_v9()
401 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, CU_ID), in event_interrupt_wq_v9()
414 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SE_ID), in event_interrupt_wq_v9()
415 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, DATA), in event_interrupt_wq_v9()
416 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SH_ID), in event_interrupt_wq_v9()
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
A Dumc_v8_7.c64 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && in umc_v8_7_ecc_info_query_correctable_error_count()
65 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) in umc_v8_7_ecc_info_query_correctable_error_count()
83 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || in umc_v8_7_ecc_info_querry_uncorrectable_error_count()
84 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || in umc_v8_7_ecc_info_querry_uncorrectable_error_count()
85 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || in umc_v8_7_ecc_info_querry_uncorrectable_error_count()
86 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) in umc_v8_7_ecc_info_querry_uncorrectable_error_count()
149 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && in umc_v8_7_ecc_info_query_error_address()
153 err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); in umc_v8_7_ecc_info_query_error_address()
259 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_GeccErrCnt, GeccErrCnt) - in umc_v8_7_query_correctable_error_count()
269 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_GeccErrCnt, GeccErrCnt) - in umc_v8_7_query_correctable_error_count()
[all …]
A Dumc_v6_7.c66 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1) in umc_v6_7_query_error_status_helper()
110 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && in umc_v6_7_ecc_info_query_correctable_error_count()
111 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) { in umc_v6_7_ecc_info_query_correctable_error_count()
122 err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); in umc_v6_7_ecc_info_query_correctable_error_count()
154 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || in umc_v6_7_ecc_info_querry_uncorrectable_error_count()
155 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || in umc_v6_7_ecc_info_querry_uncorrectable_error_count()
288 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) - in umc_v6_7_query_correctable_error_count()
298 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) - in umc_v6_7_query_correctable_error_count()
353 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || in umc_v6_7_querry_uncorrectable_error_count()
472 REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); in umc_v6_7_query_error_address()
[all …]
A Dumc_v8_10.c118 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && in umc_v8_10_query_correctable_error_count()
119 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) in umc_v8_10_query_correctable_error_count()
134 if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && in umc_v8_10_query_uncorrectable_error_count()
136 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || in umc_v8_10_query_uncorrectable_error_count()
137 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || in umc_v8_10_query_uncorrectable_error_count()
138 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || in umc_v8_10_query_uncorrectable_error_count()
139 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) in umc_v8_10_query_uncorrectable_error_count()
269 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && in umc_v8_10_query_error_address()
275 err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); in umc_v8_10_query_error_address()
372 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || in umc_v8_10_ecc_info_query_uncorrectable_error_count()
[all …]
A Dumc_v6_1.c82 return REG_GET_FIELD(rsmu_umc_val, in umc_v6_1_get_umc_index_mode_state()
204 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) - in umc_v6_1_query_correctable_error_count()
214 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) - in umc_v6_1_query_correctable_error_count()
221 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && in umc_v6_1_query_correctable_error_count()
222 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) in umc_v6_1_query_correctable_error_count()
248 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || in umc_v6_1_querry_uncorrectable_error_count()
249 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || in umc_v6_1_querry_uncorrectable_error_count()
250 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) in umc_v6_1_querry_uncorrectable_error_count()
331 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && in umc_v6_1_query_error_address()
336 lsb = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, LSB); in umc_v6_1_query_error_address()
[all …]
A Dgfxhub_v1_1.c54 seg_size = REG_GET_FIELD( in gfxhub_v1_1_get_xgmi_info()
58 REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL_ALDE, PF_MAX_REGION); in gfxhub_v1_1_get_xgmi_info()
61 seg_size = REG_GET_FIELD( in gfxhub_v1_1_get_xgmi_info()
65 REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION); in gfxhub_v1_1_get_xgmi_info()
96 REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL_ALDE, in gfxhub_v1_1_get_xgmi_info()
100 REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, in gfxhub_v1_1_get_xgmi_info()
A Dumc_v12_0.c78 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val), in umc_v12_0_is_deferred_error()
79 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Poison), in umc_v12_0_is_deferred_error()
80 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred), in umc_v12_0_is_deferred_error()
81 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC), in umc_v12_0_is_deferred_error()
82 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC), in umc_v12_0_is_deferred_error()
83 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) in umc_v12_0_is_deferred_error()
98 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || in umc_v12_0_is_uncorrectable_error()
99 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)); in umc_v12_0_is_uncorrectable_error()
531 hwid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, HardwareID); in umc_v12_0_update_ecc_status()
532 mcatype = REG_GET_FIELD(ipid, MCMP1_IPIDT0, McaType); in umc_v12_0_update_ecc_status()
[all …]
A Dumc_v12_0.h72 #define MCA_IPID_2_DIE_ID(ipid) ((REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdHi) >> 2) & 0x03)
75 (MCA_IPID_LO_2_UMC_CH(REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo)))
78 (MCA_IPID_LO_2_UMC_INST(REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo)))
81 (((REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo) & 0x1) << 2) | \
82 (REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdHi) & 0x03))
A Ddf_v4_3.c39 v0 = REG_GET_FIELD(hw_assert_msklo, in df_v4_3_query_ras_poison_mode()
41 v1 = REG_GET_FIELD(hw_assert_msklo, in df_v4_3_query_ras_poison_mode()
43 v28 = REG_GET_FIELD(hw_assert_mskhi, in df_v4_3_query_ras_poison_mode()
45 v31 = REG_GET_FIELD(hw_assert_mskhi, in df_v4_3_query_ras_poison_mode()
A Dgfx_v11_0_3.c53 if (REG_GET_FIELD(rlc_status0, RLC_RLCS_FED_STATUS_0, SDMA0_FED_ERR) || in gfx_v11_0_3_rlc_gc_fed_irq()
54 REG_GET_FIELD(rlc_status0, RLC_RLCS_FED_STATUS_0, SDMA1_FED_ERR)) in gfx_v11_0_3_rlc_gc_fed_irq()
93 if (REG_GET_FIELD(rlc_status0, RLC_RLCS_FED_STATUS_0, SDMA0_FED_ERR) || in gfx_v11_0_3_poison_consumption_handler()
94 REG_GET_FIELD(rlc_status0, RLC_RLCS_FED_STATUS_0, SDMA1_FED_ERR)) { in gfx_v11_0_3_poison_consumption_handler()
A Dsmu_v11_0_i2c.c90 if (REG_GET_FIELD(en_stat, CKSVII2C_IC_ENABLE_STATUS, IC_EN)) in smu_v11_0_i2c_enable()
189 } while (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFE) == 0); in smu_v11_0_i2c_poll_tx_status()
197 if (REG_GET_FIELD(reg, CKSVII2C_IC_INTR_STAT, R_TX_ABRT) == 1) { in smu_v11_0_i2c_poll_tx_status()
202 if (REG_GET_FIELD(reg_c_tx_abrt_source, in smu_v11_0_i2c_poll_tx_status()
208 } else if (REG_GET_FIELD(reg_c_tx_abrt_source, in smu_v11_0_i2c_poll_tx_status()
233 if (REG_GET_FIELD(reg_c_tx_abrt_source, in smu_v11_0_i2c_poll_rx_status()
251 } while (REG_GET_FIELD(reg_ic_status, CKSVII2C_IC_STATUS, RFNE) == 0); in smu_v11_0_i2c_poll_rx_status()
299 if (!REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF)) { in smu_v11_0_i2c_transmit()
423 data[bytes_received] = REG_GET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT); in smu_v11_0_i2c_receive()
470 if ((REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) && in smu_v11_0_i2c_activity_done()
[all …]
A Dsmuio_v13_0.c86 die_id = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, DIE_ID); in smuio_v13_0_get_die_id()
103 socket_id = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, SOCKET_ID); in smuio_v13_0_get_socket_id()
120 data = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, TOPOLOGY_ID); in smuio_v13_0_is_host_gpu_xgmi_supported()
137 data = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, TOPOLOGY_ID); in smuio_v13_0_get_pkg_type()
A Dsmuio_v13_0_3.c43 die_id = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, DIE_ID); in smuio_v13_0_3_get_die_id()
60 socket_id = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, SOCKET_ID); in smuio_v13_0_3_get_socket_id()
79 data = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, PKG_TYPE); in smuio_v13_0_3_get_pkg_type()
A Dgmc_v7_0.c216 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v7_0_mc_load_microcode()
222 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v7_0_mc_load_microcode()
324 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) in gmc_v7_0_mc_init()
330 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { in gmc_v7_0_mc_init()
766 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v7_0_vm_decode_fault()
771 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v7_0_vm_decode_fault()
963 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * in gmc_v7_0_get_vbios_fb_size()
964 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * in gmc_v7_0_get_vbios_fb_size()
1287 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v7_0_process_interrupt()
1292 u32 protections = REG_GET_FIELD(status, in gmc_v7_0_process_interrupt()
[all …]
A Damdgpu_mca.c46 if (REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && in amdgpu_mca_query_correctable_error_count()
47 REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) in amdgpu_mca_query_correctable_error_count()
57 if ((REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && in amdgpu_mca_query_uncorrectable_error_count()
58 (REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 || in amdgpu_mca_query_uncorrectable_error_count()
59 REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || in amdgpu_mca_query_uncorrectable_error_count()
60 REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || in amdgpu_mca_query_uncorrectable_error_count()
61 REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || in amdgpu_mca_query_uncorrectable_error_count()
62 REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) in amdgpu_mca_query_uncorrectable_error_count()
A Dgfx_v9_4.c711 sec_count = REG_GET_FIELD(data, VML2_MEM_ECC_CNTL, SEC_COUNT); in gfx_v9_4_query_utc_edc_status()
719 ded_count = REG_GET_FIELD(data, VML2_MEM_ECC_CNTL, DED_COUNT); in gfx_v9_4_query_utc_edc_status()
732 sec_count = REG_GET_FIELD(data, VML2_WALKER_MEM_ECC_CNTL, in gfx_v9_4_query_utc_edc_status()
741 ded_count = REG_GET_FIELD(data, VML2_WALKER_MEM_ECC_CNTL, in gfx_v9_4_query_utc_edc_status()
755 sec_count = REG_GET_FIELD(data, UTCL2_MEM_ECC_CNTL, SEC_COUNT); in gfx_v9_4_query_utc_edc_status()
763 ded_count = REG_GET_FIELD(data, UTCL2_MEM_ECC_CNTL, DED_COUNT); in gfx_v9_4_query_utc_edc_status()
776 sec_count = REG_GET_FIELD(data, ATC_L2_CACHE_2M_DSM_CNTL, in gfx_v9_4_query_utc_edc_status()
785 ded_count = REG_GET_FIELD(data, ATC_L2_CACHE_2M_DSM_CNTL, in gfx_v9_4_query_utc_edc_status()
799 sec_count = REG_GET_FIELD(data, ATC_L2_CACHE_4K_DSM_CNTL, in gfx_v9_4_query_utc_edc_status()
808 ded_count = REG_GET_FIELD(data, ATC_L2_CACHE_4K_DSM_CNTL, in gfx_v9_4_query_utc_edc_status()
[all …]
A Dimu_v12_0.c284 inst_index = REG_GET_FIELD(data, GRBM_GFX_INDEX, INSTANCE_INDEX); in imu_v12_0_grbm_gfx_index_remap()
289 val = REG_GET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES) << 18 | in imu_v12_0_grbm_gfx_index_remap()
290 REG_GET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES) << 19 | in imu_v12_0_grbm_gfx_index_remap()
291 REG_GET_FIELD(data, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES) << 20 | in imu_v12_0_grbm_gfx_index_remap()
292 REG_GET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX) << 21 | in imu_v12_0_grbm_gfx_index_remap()
293 REG_GET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX) << 25 | in imu_v12_0_grbm_gfx_index_remap()
A Ddf_v3_6.c228 adev->df.hash_status.hash_64k = REG_GET_FIELD(tmp, in df_v3_6_query_hashes()
231 adev->df.hash_status.hash_2m = REG_GET_FIELD(tmp, in df_v3_6_query_hashes()
234 adev->df.hash_status.hash_1g = REG_GET_FIELD(tmp, in df_v3_6_query_hashes()
650 v0 = REG_GET_FIELD(hw_assert_msklo, in df_v3_6_query_ras_poison_mode()
652 v1 = REG_GET_FIELD(hw_assert_msklo, in df_v3_6_query_ras_poison_mode()
654 v28 = REG_GET_FIELD(hw_assert_mskhi, in df_v3_6_query_ras_poison_mode()
656 v31 = REG_GET_FIELD(hw_assert_mskhi, in df_v3_6_query_ras_poison_mode()
A Dgmc_v8_0.c326 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v8_0_tonga_mc_load_microcode()
332 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v8_0_tonga_mc_load_microcode()
510 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) in gmc_v8_0_mc_init()
516 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { in gmc_v8_0_mc_init()
998 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v8_0_vm_decode_fault()
1003 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v8_0_vm_decode_fault()
1069 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * in gmc_v8_0_get_vbios_fb_size()
1070 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * in gmc_v8_0_get_vbios_fb_size()
1468 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v8_0_process_interrupt()
1473 u32 protections = REG_GET_FIELD(status, in gmc_v8_0_process_interrupt()
[all …]
A Dgfxhub_v2_0.c79 u32 cid = REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
89 REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
92 REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
95 REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
98 REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
101 REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
A Dgfxhub_v3_0_3.c81 u32 cid = REG_GET_FIELD(status, in gfxhub_v3_0_3_print_l2_protection_fault_status()
91 REG_GET_FIELD(status, in gfxhub_v3_0_3_print_l2_protection_fault_status()
94 REG_GET_FIELD(status, in gfxhub_v3_0_3_print_l2_protection_fault_status()
97 REG_GET_FIELD(status, in gfxhub_v3_0_3_print_l2_protection_fault_status()
100 REG_GET_FIELD(status, in gfxhub_v3_0_3_print_l2_protection_fault_status()
103 REG_GET_FIELD(status, in gfxhub_v3_0_3_print_l2_protection_fault_status()
A Dgfxhub_v2_1.c82 u32 cid = REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
92 REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
95 REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
98 REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
101 REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
104 REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
512 REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_MAX_REGION); in gfxhub_v2_1_get_xgmi_info()
532 REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_LFB_REGION); in gfxhub_v2_1_get_xgmi_info()
536 adev->gmc.xgmi.node_segment_size = REG_GET_FIELD( in gfxhub_v2_1_get_xgmi_info()
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dvega10_thermal.c74 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), in vega10_fan_ctrl_get_fan_speed_pwm()
76 duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS), in vega10_fan_ctrl_get_fan_speed_pwm()
104 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS), in vega10_fan_ctrl_get_fan_speed_rpm()
132 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
135 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
263 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), in vega10_fan_ctrl_set_fan_speed_pwm()

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