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Searched refs:REG_READ (Results 1 – 25 of 128) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dmub/src/
A Ddmub_dcn401.c260 return REG_READ(DMCUB_INBOX1_WPTR); in dmub_dcn401_get_inbox1_wptr()
265 return REG_READ(DMCUB_INBOX1_RPTR); in dmub_dcn401_get_inbox1_rptr()
286 return REG_READ(DMCUB_OUTBOX1_WPTR); in dmub_dcn401_get_outbox1_wptr()
303 status.all = REG_READ(DMCUB_SCRATCH0); in dmub_dcn401_is_hw_init()
330 test.all = REG_READ(DMCUB_GPINT_DATAIN1); in dmub_dcn401_is_gpint_acked()
337 return REG_READ(DMCUB_SCRATCH7); in dmub_dcn401_get_gpint_response()
359 status.all = REG_READ(DMCUB_SCRATCH0); in dmub_dcn401_get_fw_boot_status()
392 return REG_READ(DMCUB_OUTBOX0_WPTR); in dmub_dcn401_get_outbox0_wptr()
402 return REG_READ(DMCUB_TIMER_CURRENT); in dmub_dcn401_get_current_time()
497 return REG_READ(DMCUB_SCRATCH17); in dmub_dcn401_read_inbox0_ack_register()
[all …]
A Ddmub_dcn31.c248 return REG_READ(DMCUB_INBOX1_WPTR); in dmub_dcn31_get_inbox1_wptr()
253 return REG_READ(DMCUB_INBOX1_RPTR); in dmub_dcn31_get_inbox1_rptr()
274 return REG_READ(DMCUB_OUTBOX1_WPTR); in dmub_dcn31_get_outbox1_wptr()
291 status.all = REG_READ(DMCUB_SCRATCH0); in dmub_dcn31_is_hw_init()
323 test.all = REG_READ(DMCUB_GPINT_DATAIN1); in dmub_dcn31_is_gpint_acked()
330 return REG_READ(DMCUB_SCRATCH7); in dmub_dcn31_get_gpint_response()
352 status.all = REG_READ(DMCUB_SCRATCH0); in dmub_dcn31_get_fw_boot_status()
360 option.all = REG_READ(DMCUB_SCRATCH14); in dmub_dcn31_get_fw_boot_option()
383 boot_options.all = REG_READ(DMCUB_SCRATCH14); in dmub_dcn31_skip_dmub_panel_power_sequence()
398 return REG_READ(DMCUB_OUTBOX0_WPTR); in dmub_dcn31_get_outbox0_wptr()
[all …]
A Ddmub_dcn32.c277 return REG_READ(DMCUB_INBOX1_WPTR); in dmub_dcn32_get_inbox1_wptr()
282 return REG_READ(DMCUB_INBOX1_RPTR); in dmub_dcn32_get_inbox1_rptr()
303 return REG_READ(DMCUB_OUTBOX1_WPTR); in dmub_dcn32_get_outbox1_wptr()
320 status.all = REG_READ(DMCUB_SCRATCH0); in dmub_dcn32_is_hw_init()
354 return REG_READ(DMCUB_SCRATCH7); in dmub_dcn32_get_gpint_response()
376 status.all = REG_READ(DMCUB_SCRATCH0); in dmub_dcn32_get_fw_boot_status()
407 return REG_READ(DMCUB_OUTBOX0_WPTR); in dmub_dcn32_get_outbox0_wptr()
417 return REG_READ(DMCUB_TIMER_CURRENT); in dmub_dcn32_get_current_time()
513 return REG_READ(DMCUB_SCRATCH17); in dmub_dcn32_read_inbox0_ack_register()
521 index = REG_READ(DMCUB_SCRATCH15); in dmub_dcn32_save_surf_addr()
[all …]
A Ddmub_dcn35.c299 return REG_READ(DMCUB_INBOX1_WPTR); in dmub_dcn35_get_inbox1_wptr()
304 return REG_READ(DMCUB_INBOX1_RPTR); in dmub_dcn35_get_inbox1_rptr()
325 return REG_READ(DMCUB_OUTBOX1_WPTR); in dmub_dcn35_get_outbox1_wptr()
342 status.all = REG_READ(DMCUB_SCRATCH0); in dmub_dcn35_is_hw_init()
376 return REG_READ(DMCUB_SCRATCH7); in dmub_dcn35_get_gpint_response()
398 status.all = REG_READ(DMCUB_SCRATCH0); in dmub_dcn35_get_fw_boot_status()
406 option.all = REG_READ(DMCUB_SCRATCH14); in dmub_dcn35_get_fw_boot_option()
451 return REG_READ(DMCUB_OUTBOX0_WPTR); in dmub_dcn35_get_outbox0_wptr()
461 return REG_READ(DMCUB_TIMER_CURRENT); in dmub_dcn35_get_current_time()
560 return REG_READ(DMCUB_SCRATCH17); in dmub_dcn35_read_inbox0_ack_register()
[all …]
A Ddmub_dcn20.c288 return REG_READ(DMCUB_INBOX1_WPTR); in dmub_dcn20_get_inbox1_wptr()
293 return REG_READ(DMCUB_INBOX1_RPTR); in dmub_dcn20_get_inbox1_rptr()
319 return REG_READ(DMCUB_OUTBOX1_WPTR); in dmub_dcn20_get_outbox1_wptr()
341 return REG_READ(DMCUB_OUTBOX0_WPTR); in dmub_dcn20_get_outbox0_wptr()
379 test.all = REG_READ(DMCUB_GPINT_DATAIN1); in dmub_dcn20_is_gpint_acked()
386 return REG_READ(DMCUB_SCRATCH7); in dmub_dcn20_get_gpint_response()
393 status.all = REG_READ(DMCUB_SCRATCH0); in dmub_dcn20_get_fw_boot_status()
407 boot_options.all = REG_READ(DMCUB_SCRATCH14); in dmub_dcn20_skip_dmub_panel_power_sequence()
414 return REG_READ(DMCUB_TIMER_CURRENT); in dmub_dcn20_get_current_time()
429 diag_data->scratch[0] = REG_READ(DMCUB_SCRATCH0); in dmub_dcn20_get_diagnostic_data()
[all …]
/linux/drivers/gpu/drm/gma500/
A Dcdv_device.c36 REG_READ(vga_reg); in cdv_disable_vga()
51 if (REG_READ(SDVOB) & SDVO_DETECTED) { in cdv_output_init()
53 if (REG_READ(DP_B) & DP_DETECTED) in cdv_output_init()
57 if (REG_READ(SDVOC) & SDVO_DETECTED) { in cdv_output_init()
59 if (REG_READ(DP_C) & DP_DETECTED) in cdv_output_init()
76 u32 max = REG_READ(BLC_PWM_CTL); in cdv_get_max_backlight()
251 regs->cdv.saveADPA = REG_READ(ADPA); in cdv_save_display_registers()
304 temp = REG_READ(DPLL_A); in cdv_restore_display_registers()
307 REG_READ(DPLL_A); in cdv_restore_display_registers()
310 temp = REG_READ(DPLL_B); in cdv_restore_display_registers()
[all …]
A Dgma_display.c125 REG_READ(map->base); in gma_pipe_set_base()
128 REG_READ(map->base); in gma_pipe_set_base()
130 REG_READ(map->surf); in gma_pipe_set_base()
226 REG_READ(map->dpll); in gma_crtc_dpms()
230 REG_READ(map->dpll); in gma_crtc_dpms()
234 REG_READ(map->dpll); in gma_crtc_dpms()
295 REG_READ(map->base); in gma_crtc_dpms()
302 REG_READ(map->conf); in gma_crtc_dpms()
641 REG_READ(map->fp0); in gma_crtc_restore()
644 REG_READ(map->fp1); in gma_crtc_restore()
[all …]
A Dcdv_intel_display.c152 *val = REG_READ(SB_DATA); in cdv_sb_read()
203 REG_READ(DPIO_CFG); in cdv_sb_reset()
476 REG_READ(FW_BLC_SELF); in cdv_disable_sr()
484 REG_READ(OV_OVADD); in cdv_disable_sr()
500 fw = REG_READ(DSPFW1); in cdv_update_wm()
507 fw = REG_READ(DSPFW2); in cdv_update_wm()
536 REG_READ(FW_BLC_SELF); in cdv_update_wm()
723 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
755 REG_READ(LVDS); in cdv_intel_crtc_mode_set()
769 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
[all …]
A Dpsb_intel_lvds.c67 ret = REG_READ(BLC_PWM_CTL); in psb_intel_lvds_get_max_backlight()
189 blc_pwm_ctl = REG_READ(BLC_PWM_CTL); in psb_intel_lvds_set_backlight()
220 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in psb_intel_lvds_set_power()
223 pp_status = REG_READ(PP_STATUS); in psb_intel_lvds_set_power()
231 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in psb_intel_lvds_set_power()
234 pp_status = REG_READ(PP_STATUS); in psb_intel_lvds_set_power()
261 lvds_priv->savePP_ON = REG_READ(LVDSPP_ON); in psb_intel_lvds_save()
263 lvds_priv->saveLVDS = REG_READ(LVDS); in psb_intel_lvds_save()
322 pp_status = REG_READ(PP_STATUS); in psb_intel_lvds_restore()
328 pp_status = REG_READ(PP_STATUS); in psb_intel_lvds_restore()
[all …]
A Doaktrail_hdmi.c295 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
311 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
369 REG_READ(pipeconf_reg); in oaktrail_crtc_hdmi_mode_set()
372 REG_READ(PCH_PIPEBCONF); in oaktrail_crtc_hdmi_mode_set()
398 REG_READ(DSPBCNTR); in oaktrail_crtc_hdmi_dpms()
401 REG_READ(DSPBSURF); in oaktrail_crtc_hdmi_dpms()
408 REG_READ(PIPEBCONF); in oaktrail_crtc_hdmi_dpms()
415 REG_READ(PCH_PIPEBCONF); in oaktrail_crtc_hdmi_dpms()
450 REG_READ(PIPEBCONF); in oaktrail_crtc_hdmi_dpms()
457 REG_READ(PCH_PIPEBCONF); in oaktrail_crtc_hdmi_dpms()
[all …]
A Dpsb_intel_display.c197 pipeconf = REG_READ(map->conf); in psb_intel_crtc_mode_set()
221 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
230 u32 lvds = REG_READ(LVDS); in psb_intel_crtc_mode_set()
251 REG_READ(LVDS); in psb_intel_crtc_mode_set()
256 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
263 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
288 REG_READ(map->conf); in psb_intel_crtc_mode_set()
317 dpll = REG_READ(map->dpll); in psb_intel_crtc_clock_get()
319 fp = REG_READ(map->fp0); in psb_intel_crtc_clock_get()
321 fp = REG_READ(map->fp1); in psb_intel_crtc_clock_get()
[all …]
A Dcdv_intel_dp.c388 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_on()
392 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_on()
402 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_off()
406 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_off()
421 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_on()
426 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_on()
446 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_off()
459 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_off()
483 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_backlight_on()
499 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_backlight_off()
[all …]
A Dintel_i2c.c29 val = REG_READ(chan->reg); in get_clock()
39 val = REG_READ(chan->reg); in get_data()
51 REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE | in set_clock()
71 REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE | in set_data()
/linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/
A Ddcn20_hubbub.c517 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A); in hubbub2_wm_read_state()
521 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A); in hubbub2_wm_read_state()
522 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A); in hubbub2_wm_read_state()
528 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B); in hubbub2_wm_read_state()
532 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B); in hubbub2_wm_read_state()
533 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B); in hubbub2_wm_read_state()
539 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C); in hubbub2_wm_read_state()
543 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C); in hubbub2_wm_read_state()
544 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C); in hubbub2_wm_read_state()
550 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D); in hubbub2_wm_read_state()
[all …]
/linux/drivers/net/wireless/ath/ath9k/
A Dar9002_calib.c131 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_iqcal_collect()
133 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_iqcal_collect()
150 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_adc_gaincal_collect()
152 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_adc_gaincal_collect()
154 REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9002_hw_adc_gaincal_collect()
567 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
570 regVal = REG_READ(ah, 0x9808); in ar9285_hw_pa_cal()
595 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
599 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
632 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
[all …]
A Dar9003_calib.c183 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9003_hw_iqcal_collect()
185 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9003_hw_iqcal_collect()
271 REG_READ(ah, offset_array[i])); in ar9003_hw_iqcalibrate()
288 REG_READ(ah, offset_array[i])); in ar9003_hw_iqcalibrate()
293 REG_READ(ah, offset_array[i])); in ar9003_hw_iqcalibrate()
306 REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0)); in ar9003_hw_iqcalibrate()
414 temp = REG_READ(ah, AR_PHY_65NM_CH0_BB3); in ar9003_hw_dynamic_osdac_selection()
418 temp = REG_READ(ah, AR_PHY_65NM_CH1_BB3); in ar9003_hw_dynamic_osdac_selection()
422 temp = REG_READ(ah, AR_PHY_65NM_CH2_BB3); in ar9003_hw_dynamic_osdac_selection()
1088 if (REG_READ(ah, txiqcal_status[i]) & in ar9003_hw_tx_iq_cal_post_proc()
[all …]
A Dar9003_wow.c48 REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW)); in ath9k_hw_set_powermode_wow_sleep()
53 if (!REG_READ(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL)) in ath9k_hw_set_powermode_wow_sleep()
56 if (!(REG_READ(ah, AR_NDP2_TIMER_MODE) & in ath9k_hw_set_powermode_wow_sleep()
192 rval = REG_READ(ah, AR_WOW_PATTERN); in ath9k_hw_wow_wakeup()
213 rval = REG_READ(ah, AR_MAC_PCU_WOW4); in ath9k_hw_wow_wakeup()
236 AR_WOW_CLEAR_EVENTS(REG_READ(ah, AR_WOW_PATTERN))); in ath9k_hw_wow_wakeup()
256 u32 dc = REG_READ(ah, AR_DIRECT_CONNECT); in ath9k_hw_wow_wakeup()
281 wa_reg = REG_READ(ah, AR_WA(ah)); in ath9k_hw_wow_set_arwr_reg()
364 keep_alive = REG_READ(ah, AR_WOW_KEEP_ALIVE); in ath9k_hw_wow_enable()
395 magic_pattern = REG_READ(ah, AR_WOW_PATTERN); in ath9k_hw_wow_enable()
[all …]
A Dar9002_mac.c46 isr = REG_READ(ah, AR_ISR); in ar9002_hw_get_isr()
59 isr = REG_READ(ah, AR_ISR); in ar9002_hw_get_isr()
65 isr2 = REG_READ(ah, AR_ISR_S2); in ar9002_hw_get_isr()
88 isr = REG_READ(ah, AR_ISR_RAC); in ar9002_hw_get_isr()
109 s0_s = REG_READ(ah, AR_ISR_S0_S); in ar9002_hw_get_isr()
110 s1_s = REG_READ(ah, AR_ISR_S1_S); in ar9002_hw_get_isr()
112 s0_s = REG_READ(ah, AR_ISR_S0); in ar9002_hw_get_isr()
114 s1_s = REG_READ(ah, AR_ISR_S1); in ar9002_hw_get_isr()
141 s5_s = REG_READ(ah, AR_ISR_S5_S(ah)); in ar9002_hw_get_isr()
143 s5_s = REG_READ(ah, AR_ISR_S5); in ar9002_hw_get_isr()
[all …]
A Dar9002_phy.c76 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL); in ar9002_hw_set_channel()
98 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); in ar9002_hw_set_channel()
225 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); in ar9002_hw_spur_mitigate()
298 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4), in ar9002_olc_init()
336 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR); in ar9002_hw_do_getnf()
339 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR); in ar9002_hw_do_getnf()
346 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR); in ar9002_hw_do_getnf()
383 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ar9002_hw_antdiv_comb_conf_get()
400 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ar9002_hw_antdiv_comb_conf_set()
455 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ar9002_hw_set_bt_ant_diversity()
[all …]
A Dmac.c48 return REG_READ(ah, AR_QTXDP(q)); in ath9k_hw_gettxbuf()
72 if (REG_READ(ah, AR_Q_TXE) & (1 << q)) in ath9k_hw_numtxpending()
114 txcfg = REG_READ(ah, AR_TXCFG); in ath9k_hw_updatetxtriglevel()
653 reg = REG_READ(ah, AR_OBS_BUS_1); in ath9k_hw_setrxabort()
730 REG_READ(ah, AR_CR), in ath9k_hw_stopdmarecv()
731 REG_READ(ah, AR_DIAG_SW), in ath9k_hw_stopdmarecv()
732 REG_READ(ah, AR_DMADBG_7)); in ath9k_hw_stopdmarecv()
787 (void) REG_READ(ah, AR_IER); in ath9k_hw_kill_interrupts()
834 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER)); in __ath9k_hw_enable_interrupts()
849 REG_READ(ah, AR_INTR_PRIO_ASYNC_MASK(ah))); in __ath9k_hw_enable_interrupts()
[all …]
A Dar9003_mci.c39 if (!(REG_READ(ah, address) & bit_position)) { in ar9003_mci_wait_for_interrupt()
71 REG_READ(ah, AR_MCI_INTERRUPT_RAW), in ar9003_mci_wait_for_interrupt()
72 REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW)); in ar9003_mci_wait_for_interrupt()
238 REG_READ(ah, AR_MCI_INTERRUPT_RAW)); in ar9003_mci_prep_interface()
986 regval = REG_READ(ah, AR_MCI_COMMAND2); in ar9003_mci_reset()
1177 regval = REG_READ(ah, AR_BTCOEX_CTRL); in ar9003_mci_send_message()
1298 value = REG_READ(ah, AR_BTCOEX_CTRL); in ar9003_mci_state()
1314 value = MS(REG_READ(ah, AR_MCI_RX_STATUS), in ar9003_mci_state()
1320 value = MS(REG_READ(ah, AR_MCI_RX_STATUS), in ar9003_mci_state()
1340 if ((REG_READ(ah, AR_GLB_GPIO_CONTROL) & in ar9003_mci_state()
[all …]
/linux/drivers/net/wireless/ath/
A Dhw.c23 #define REG_READ (common->ops->read) macro
124 id1 = REG_READ(ah, AR_STA_ID1) & ~AR_STA_ID1_SADH_MASK; in ath_hw_setbssidmask()
151 cycles = REG_READ(ah, AR_CCCNT); in ath_hw_cycle_counters_update()
152 busy = REG_READ(ah, AR_RCCNT); in ath_hw_cycle_counters_update()
153 rx = REG_READ(ah, AR_RFCNT); in ath_hw_cycle_counters_update()
154 tx = REG_READ(ah, AR_TFCNT); in ath_hw_cycle_counters_update()
/linux/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_panel_cntl.c57 REG_READ(BL_PWM_PERIOD_CNTL); in dce_get_16_bit_backlight_from_pwm()
61 REG_READ(BL_PWM_CNTL); in dce_get_16_bit_backlight_from_pwm()
113 REG_READ(BL_PWM_CNTL); in dce_panel_cntl_hw_init()
115 REG_READ(BL_PWM_CNTL2); in dce_panel_cntl_hw_init()
117 REG_READ(BL_PWM_PERIOD_CNTL); in dce_panel_cntl_hw_init()
131 value = REG_READ(BIOS_SCRATCH_2); in dce_panel_cntl_hw_init()
178 REG_READ(BL_PWM_CNTL); in dce_store_backlight_level()
180 REG_READ(BL_PWM_CNTL2); in dce_store_backlight_level()
182 REG_READ(BL_PWM_PERIOD_CNTL); in dce_store_backlight_level()
/linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/
A Ddcn10_hubbub.c52 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A); in hubbub1_wm_read_state()
55 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A); in hubbub1_wm_read_state()
56 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A); in hubbub1_wm_read_state()
62 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B); in hubbub1_wm_read_state()
65 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B); in hubbub1_wm_read_state()
66 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B); in hubbub1_wm_read_state()
72 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C); in hubbub1_wm_read_state()
75 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C); in hubbub1_wm_read_state()
76 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C); in hubbub1_wm_read_state()
86 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D); in hubbub1_wm_read_state()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn301/
A Ddcn301_panel_cntl.c128 REG_READ(BL_PWM_CNTL); in dcn301_panel_cntl_hw_init()
130 REG_READ(BL_PWM_CNTL2); in dcn301_panel_cntl_hw_init()
132 REG_READ(BL_PWM_PERIOD_CNTL); in dcn301_panel_cntl_hw_init()
185 REG_READ(BL_PWM_CNTL); in dcn301_store_backlight_level()
187 REG_READ(BL_PWM_CNTL2); in dcn301_store_backlight_level()
189 REG_READ(BL_PWM_PERIOD_CNTL); in dcn301_store_backlight_level()

Completed in 61 milliseconds

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