Home
last modified time | relevance | path

Searched refs:REG_STRUCT (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/irq/dcn35/
A Dirq_service_dcn35.c209 REG_STRUCT[base + reg_num].enable_mask = \
211 REG_STRUCT[base + reg_num].enable_value[0] = \
216 REG_STRUCT[base + reg_num].ack_mask = \
218 REG_STRUCT[base + reg_num].ack_value = \
223 REG_STRUCT[base].enable_mask = \
225 REG_STRUCT[base].enable_value[0] = \
227 REG_STRUCT[base].enable_value[1] = \
229 REG_STRUCT[base].ack_reg = SRI_DMUB(reg2),\
230 REG_STRUCT[base].ack_mask = \
232 REG_STRUCT[base].ack_value = \
[all …]
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn351/
A Dirq_service_dcn351.c188 REG_STRUCT[base + reg_num].enable_mask = \
190 REG_STRUCT[base + reg_num].enable_value[0] = \
195 REG_STRUCT[base + reg_num].ack_mask = \
197 REG_STRUCT[base + reg_num].ack_value = \
202 REG_STRUCT[base].enable_mask = \
204 REG_STRUCT[base].enable_value[0] = \
206 REG_STRUCT[base].enable_value[1] = \
208 REG_STRUCT[base].ack_reg = SRI_DMUB(reg2),\
209 REG_STRUCT[base].ack_mask = \
211 REG_STRUCT[base].ack_value = \
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/
A Ddcn35_resource.c817 #undef REG_STRUCT in dcn35_dpp_create()
849 #undef REG_STRUCT in dcn35_opp_create()
874 #undef REG_STRUCT in dcn31_aux_engine_create()
937 #undef REG_STRUCT in dcn31_i2c_hw_create()
960 #undef REG_STRUCT in dcn35_mpc_create()
984 #undef REG_STRUCT in dcn35_hubbub_create()
988 #undef REG_STRUCT in dcn35_hubbub_create()
1039 #undef REG_STRUCT in dcn35_timing_generator_create()
1080 #undef REG_STRUCT in dcn35_link_encoder_create()
1088 #undef REG_STRUCT in dcn35_link_encoder_create()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/
A Ddcn351_resource.c797 #undef REG_STRUCT in dcn35_dpp_create()
829 #undef REG_STRUCT in dcn35_opp_create()
854 #undef REG_STRUCT in dcn31_aux_engine_create()
917 #undef REG_STRUCT in dcn31_i2c_hw_create()
940 #undef REG_STRUCT in dcn35_mpc_create()
964 #undef REG_STRUCT in dcn35_hubbub_create()
968 #undef REG_STRUCT in dcn35_hubbub_create()
1019 #undef REG_STRUCT in dcn35_timing_generator_create()
1060 #undef REG_STRUCT in dcn35_link_encoder_create()
1068 #undef REG_STRUCT in dcn35_link_encoder_create()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/
A Ddcn321_resource.c750 #undef REG_STRUCT in dcn321_aux_engine_create()
790 #undef REG_STRUCT in dcn321_i2c_hw_create()
838 #undef REG_STRUCT in dcn321_hubbub_create()
842 #undef REG_STRUCT in dcn321_hubbub_create()
893 #undef REG_STRUCT in dcn321_hubp_create()
925 #undef REG_STRUCT in dcn321_dpp_create()
952 #undef REG_STRUCT in dcn321_mpc_create()
977 #undef REG_STRUCT in dcn321_opp_create()
1000 #undef REG_STRUCT in dcn321_timing_generator_create()
1041 #undef REG_STRUCT in dcn321_link_encoder_create()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/
A Ddcn401_resource.c750 #undef REG_STRUCT in dcn401_aux_engine_create()
789 #undef REG_STRUCT in dcn401_i2c_hw_create()
837 #undef REG_STRUCT in dcn401_hubbub_create()
841 #undef REG_STRUCT in dcn401_hubbub_create()
891 #undef REG_STRUCT in dcn401_hubp_create()
923 #undef REG_STRUCT in dcn401_dpp_create()
950 #undef REG_STRUCT in dcn401_mpc_create()
975 #undef REG_STRUCT in dcn401_opp_create()
997 #undef REG_STRUCT in dcn401_timing_generator_create()
1038 #undef REG_STRUCT in dcn401_link_encoder_create()
[all …]
/linux/drivers/gpu/drm/amd/display/dmub/src/
A Ddmub_dcn351.c19 #define REG_STRUCT regs in dmub_srv_dcn351_regs_init() macro
21 #define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg); in dmub_srv_dcn351_regs_init()
26 #define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field); in dmub_srv_dcn351_regs_init()
30 #define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field); in dmub_srv_dcn351_regs_init()
33 #undef REG_STRUCT in dmub_srv_dcn351_regs_init()
A Ddmub_dcn32.c44 #define REG_STRUCT regs in dmub_srv_dcn32_regs_init() macro
46 #define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg); in dmub_srv_dcn32_regs_init()
51 #define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field); in dmub_srv_dcn32_regs_init()
55 #define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field); in dmub_srv_dcn32_regs_init()
59 #undef REG_STRUCT in dmub_srv_dcn32_regs_init()
A Ddmub_dcn35.c42 #define REG_STRUCT regs in dmub_srv_dcn35_regs_init() macro
44 #define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg); in dmub_srv_dcn35_regs_init()
49 #define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field); in dmub_srv_dcn35_regs_init()
53 #define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field); in dmub_srv_dcn35_regs_init()
56 #undef REG_STRUCT in dmub_srv_dcn35_regs_init()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
A Ddcn32_resource.c754 #undef REG_STRUCT in dcn32_aux_engine_create()
794 #undef REG_STRUCT in dcn32_i2c_hw_create()
842 #undef REG_STRUCT in dcn32_hubbub_create()
846 #undef REG_STRUCT in dcn32_hubbub_create()
897 #undef REG_STRUCT in dcn32_hubp_create()
929 #undef REG_STRUCT in dcn32_dpp_create()
956 #undef REG_STRUCT in dcn32_mpc_create()
981 #undef REG_STRUCT in dcn32_opp_create()
1004 #undef REG_STRUCT in dcn32_timing_generator_create()
1045 #undef REG_STRUCT in dcn32_link_encoder_create()
[all …]

Completed in 42 milliseconds