Home
last modified time | relevance | path

Searched refs:RENDER_RING_BASE (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/gpu/drm/i915/gvt/
A Dmmio_context.c58 {RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */
62 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
63 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
64 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
65 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
66 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
67 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
68 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
69 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
70 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
[all …]
A Dhandlers.c2163 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
2219 MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL); in init_generic_mmio_info()
2788 MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS, in init_bxt_mmio_info()
/linux/drivers/gpu/drm/i915/
A Di915_cmd_parser.c619 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
620 REG64_IDX(MI_PREDICATE_SRC0, RENDER_RING_BASE),
621 REG64_IDX(MI_PREDICATE_SRC1, RENDER_RING_BASE),
651 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 0),
652 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 1),
653 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 2),
654 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 3),
655 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 4),
656 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 5),
677 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
[all …]
A Di915_ioctl.c32 .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
33 .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
A Dintel_clock_gating.c444 intel_uncore_write(&i915->uncore, RING_PSMI_CTL(RENDER_RING_BASE), in bdw_init_clock_gating()
581 intel_uncore_write(&i915->uncore, RING_PSMI_CTL(RENDER_RING_BASE), in chv_init_clock_gating()
652 intel_uncore_write(&i915->uncore, ECOSKPD(RENDER_RING_BASE), in gen3_init_clock_gating()
656 intel_uncore_write(&i915->uncore, ECOSKPD(RENDER_RING_BASE), in gen3_init_clock_gating()
A Dintel_gvt_mmio_table.c44 MMIO_F(prefix(RENDER_RING_BASE), s); \
81 MMIO_D(CCID(RENDER_RING_BASE)); in iterate_generic_mmio()
606 MMIO_D(ECOSKPD(RENDER_RING_BASE)); in iterate_generic_mmio()
1249 MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40); in iterate_bxt_mmio()
A Di915_perf.c1956 MI_PREDICATE_RESULT_1(RENDER_RING_BASE); in alloc_noa_wait()
2762 GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE), in lrc_configure_all_contexts()
A Dintel_uncore.c1751 __raw_uncore_write32(uncore, RING_MI_MODE(RENDER_RING_BASE), 0); in ilk_dummy_write()
A Di915_reg.h289 #define RENDER_RING_BASE 0x02000 macro
/linux/drivers/gpu/drm/xe/
A Dxe_wa.c260 XE_RTP_ACTIONS(SET(FF_THREAD_MODE(RENDER_RING_BASE),
281 XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1(RENDER_RING_BASE),
290 XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1(RENDER_RING_BASE),
298 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
307 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
316 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
406 XE_RTP_ACTIONS(SET(RING_HWSTAM(RENDER_RING_BASE), ~0))
581 XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(RENDER_RING_BASE),
688 XE_RTP_ACTIONS(SET(INSTPM(RENDER_RING_BASE), ENABLE_SEMAPHORE_POLL_BIT))
A Dxe_reg_whitelist.c65 XE_RTP_ACTIONS(WHITELIST(CSBE_DEBUG_STATUS(RENDER_RING_BASE), 0))
A Dxe_hw_engine.c58 .mmio_base = RENDER_RING_BASE,
/linux/drivers/gpu/drm/i915/gt/
A Dintel_engine_regs.h35 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
36 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
37 #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
A Dintel_workarounds.c354 wa_masked_en(wal, RING_MI_MODE(RENDER_RING_BASE), ASYNC_FLIP_PERF_DISABLE); in gen8_ctx_workarounds_init()
2297 RING_PSMI_CTL(RENDER_RING_BASE), in rcs_engine_wa_init()
2549 RING_MODE_GEN7(RENDER_RING_BASE), in rcs_engine_wa_init()
2587 RING_MI_MODE(RENDER_RING_BASE), in rcs_engine_wa_init()
2646 wa_add(wal, RING_MI_MODE(RENDER_RING_BASE), in rcs_engine_wa_init()
2662 wa_add(wal, ECOSKPD(RENDER_RING_BASE), in rcs_engine_wa_init()
A Dintel_gt.c254 intel_uncore_write(uncore, IPEIR(RENDER_RING_BASE), 0); in intel_gt_clear_error_registers()
454 RING_TAIL(RENDER_RING_BASE)); in intel_gt_flush_ggtt_writes()
A Dintel_rc6.c471 if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT(RENDER_RING_BASE)) & IDLE_TIME_MASK) > 1 && in bxt_check_bios_rc6_setup()
A Dintel_engine_cs.c68 { .graphics_ver = 1, .base = RENDER_RING_BASE }
/linux/drivers/gpu/drm/xe/regs/
A Dxe_engine_regs.h18 #define RENDER_RING_BASE 0x02000 macro

Completed in 69 milliseconds