| /linux/drivers/scsi/pcmcia/ |
| A D | nsp_io.h | 21 unsigned int Register,
24 unsigned int Register);
48 unsigned int Register) in nsp_index_read() argument
55 unsigned int Register, in nsp_index_write() argument
68 unsigned int Register, in nsp_multi_read_1() argument
87 unsigned int Register, in nsp_multi_read_2() argument
106 unsigned int Register, in nsp_multi_read_4() argument
125 unsigned int Register, in nsp_multi_write_1() argument
143 unsigned int Register, in nsp_multi_write_2() argument
220 unsigned int Register, in nsp_mmio_multi_read_4() argument
[all …]
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| /linux/Documentation/scsi/ |
| A D | hptiop.rst | 8 Controller Register Map
14 BAR0 offset Register
21 BAR2 offset Register
23 0x10 Inbound Message Register 0
24 0x14 Inbound Message Register 1
27 0x20 Inbound Doorbell Register
39 BAR0 offset Register
57 BAR0 offset Register
66 BAR1 offset Register
81 BAR0 offset Register
[all …]
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| /linux/Documentation/driver-api/mmc/ |
| A D | mmc-dev-attrs.rst | 20 cid Card Identification Register
21 csd Card Specific Data Register
22 scr SD Card Configuration Register (SD only)
23 date Manufacturing Date (from CID Register)
28 manfid Manufacturer ID (from CID Register)
29 name Product Name (from CID Register)
30 oemid OEM/Application ID (from CID Register)
31 prv Product Revision (from CID Register)
33 serial Product Serial Number (from CID Register)
38 ocr Operation Conditions Register
[all …]
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| /linux/Documentation/devicetree/bindings/phy/ |
| A D | starfive,jh7110-pcie-phy.yaml | 26 - description: phandle to System Register Controller sys_syscon node.
29 The phandle to System Register Controller syscon node and the PHY connect offset
36 - description: phandle to System Register Controller stg_syscon node.
40 The phandle to System Register Controller syscon node and the offset
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| /linux/arch/arm/include/debug/ |
| A D | at91.S | 19 strb \rd, [\rx, #(AT91_DBGU_THR)] @ Write to Transmitter Holding Register
23 1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
32 1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
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| A D | vf.S | 23 strb \rd, [\rx, #0x7] @ Data Register
27 1001: ldrb \rd, [\rx, #0x4] @ Status Register 1
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| A D | stm32.S | 34 1001: ldr \rd, [\rx, #(STM32_USART_SR_OFF)] @ Read Status Register
40 1001: ldr \rd, [\rx, #(STM32_USART_SR_OFF)] @ Read Status Register
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| /linux/Documentation/devicetree/bindings/rtc/ |
| A D | rtc-cmos.txt | 11 called "Register B".
13 called "Register A".
15 "Register A" and "B" are usually initialized by the firmware (BIOS for
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| /linux/Documentation/devicetree/bindings/hwinfo/ |
| A D | renesas,prr.yaml | 7 title: Renesas Product Register
14 Most Renesas ARM SoCs have a Product Register or Boundary Scan ID
15 Register that allows to retrieve SoC product and revision information.
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| /linux/Documentation/devicetree/bindings/gpio/ |
| A D | gpio-mmio.yaml | 43 Register to READ the value of the GPIO lines. If GPIO line is high,
48 Register to SET the value of the GPIO lines. Setting a bit in this
51 Register to CLEAR the value of the GPIO lines. Setting a bit in this
56 Register to set the line as OUTPUT. Setting a bit in this register
60 Register to set this line as INPUT. Setting a bit in this register
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| /linux/Documentation/gpu/xe/ |
| A D | xe_gt_mcr.rst | 4 GT Multicast/Replicated (MCR) Register Support
8 :doc: GT Multicast/Replicated (MCR) Register Support
|
| A D | xe_rtp.rst | 4 Register Table Processing
8 :doc: Register Table Processing
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| /linux/Documentation/devicetree/bindings/pinctrl/ |
| A D | fsl,imx27-pinctrl.txt | 24 Registers: GIUS (GPIO In Use), GPR (General Purpose Register)
30 Register: DDIR
40 3 - Data Register
47 1 - Interrupt Status Register
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| /linux/Documentation/devicetree/bindings/sound/ |
| A D | alc5623.txt | 11 Register. If absent or has the value of 0, the
15 Control Register. If absent or has value 0, the
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| /linux/Documentation/devicetree/bindings/memory-controllers/ddr/ |
| A D | jedec,lpddr-props.yaml | 39 Revision IDs read from Mode Register 6 and 7. One byte per uint32 cell (i.e. <MR6 MR7>).
48 Density in megabits of SDRAM chip. Decoded from Mode Register 8.
68 IO bus width in bits of SDRAM chip. Decoded from Mode Register 8.
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| /linux/Documentation/devicetree/bindings/net/ |
| A D | fsl,enetc-ierb.yaml | 7 title: Integrated Endpoint Register Block
10 The fsl_enetc driver can probe on the Integrated Endpoint Register Block,
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| /linux/Documentation/devicetree/bindings/display/imx/ |
| A D | fsl,imx-lcdc.yaml | 56 Override value for DMA Control Register
61 Contrast Control Register value.
66 LCDC Sharp Configuration Register value.
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| /linux/rust/kernel/net/phy/ |
| A D | reg.rs | 43 pub trait Register: private::Sealed { interface
104 impl Register for C22 {
196 impl Register for C45 {
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| /linux/Documentation/devicetree/bindings/perf/ |
| A D | arm,coresight-pmu.yaml | 18 - description: Register page 0
19 - description: Register page 1, if the PMU implements the dual-page extension
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| /linux/Documentation/ABI/testing/ |
| A D | debugfs-intel-iommu | 13 IOMMU: dmar0 Register Base Address: 26be37000
24 IOMMU: dmar1 Register Base Address: fed90000
35 IOMMU: dmar2 Register Base Address: fed91000
191 IOMMU: dmar0 Register Base Address: 26be37000
200 IOMMU: dmar2 Register Base Address: fed91000
213 IOMMU: dmar0 Register Base Address: 26be37000
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| /linux/drivers/mtd/chips/ |
| A D | Kconfig | 167 erased. Each Protection Register can be accessed multiple times to
170 Each Protection Register has an associated Lock Register bit. When a
171 Lock Register bit is programmed, the associated Protection Register
173 because the Lock Register bits themselves are OTP, when programmed,
174 Lock Register bits cannot be erased. Therefore, when a Protection
175 Register is locked, it cannot be unlocked.
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| /linux/Documentation/arch/m68k/ |
| A D | buddha-driver.rst | 10 Register map of the Buddha IDE controller and the
45 $7fe Speed-select Register: Read & Write
48 $800-$8ff IDE-Select 0 (Port 0, Register set 0)
50 $900-$9ff IDE-Select 1 (Port 0, Register set 1)
52 $a00-$aff IDE-Select 2 (Port 1, Register set 0)
54 $b00-$bff IDE-Select 3 (Port 1, Register set 1)
56 $c00-$cff IDE-Select 4 (Port 2, Register set 0,
59 $d00-$dff IDE-Select 5 (Port 3, Register set 1,
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| /linux/drivers/crypto/caam/ |
| A D | Kconfig | 97 bool "Register algorithm implementations with the Crypto API"
128 bool "Register hash algorithm implementations with Crypto API"
137 bool "Register public key cryptography implementations with Crypto API"
146 bool "Register caam device for hwrng API"
155 bool "Register Pseudo random number generation implementation with Crypto API"
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| /linux/Documentation/arch/parisc/ |
| A D | registers.rst | 2 Register Usage for Linux/PA-RISC
24 CR19 Interrupt Instruction Register
25 CR20 Interrupt Space Register
26 CR21 Interrupt Offset Register
108 Register usage notes, originally from John Marvin, with some additional
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| /linux/drivers/soc/rockchip/ |
| A D | Kconfig | 9 bool "Rockchip General Register Files support" if COMPILE_TEST
12 The General Register Files are a central component providing
|