Searched refs:SCLK (Results 1 – 25 of 30) sorted by relevance
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| /linux/Documentation/iio/ |
| A D | ad4000.rst | 62 +--------------------| SCLK |
87 +--------------------| SCLK |
104 +--------------------| SCLK |
130 +--------------------| SCLK |
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| A D | ad7944.rst | 43 +--------------------| SCLK |
65 +--------------------| SCLK |
85 +-------------------------+--------------------| SCLK |
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| A D | ad4695.rst | 44 | SCLK |<--------| SCLK |
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| /linux/drivers/spi/ |
| A D | spi-lm70llp.c | 66 #define SCLK 0x40 macro
116 parport_write_data(pp->port, data | SCLK); in clkHigh()
123 parport_write_data(pp->port, data & ~SCLK); in clkLow()
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| /linux/Documentation/devicetree/bindings/iio/resolver/ |
| A D | adi,ad2s90.yaml | 27 application of SCLK, as also specified. And since the delay is not
28 implemented in the spi code, to satisfy it, SCLK's period should be at
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| /linux/Documentation/devicetree/bindings/sound/ |
| A D | ti,pcm512x.yaml | 37 description: A clock specifier for the clock connected as SCLK. If this is
55 external connection from the pll-out pin to the SCLK pin is assumed.
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| A D | cs35l34.txt | 45 SCLK. Otherwise, data is on the falling edge of SCLK.
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| A D | fsl,sgtl5000.yaml | 71 The SCLK pad strength. Possible values are: 0, 1, 2 and 3 as per the
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| /linux/include/dt-bindings/clock/ |
| A D | microchip,pic32-clock.h | 18 #define SCLK 7 macro
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| /linux/Documentation/devicetree/bindings/spi/ |
| A D | spi_oc_tiny.txt | 9 the input clock to SCLK.
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| A D | spi-rockchip.yaml | 72 Nano seconds to delay after the SCLK edge before sampling Rx data
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| /linux/Documentation/hwmon/ |
| A D | lm70.rst | 45 the driver accesses the LM70 using SPI communication: 16 SCLK cycles
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| /linux/drivers/clk/microchip/ |
| A D | clk-pic32mzda.c | 210 clks[SCLK] = pic32_sys_clk_register(&sys_mux_clk, core); in pic32mzda_clk_probe()
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| /linux/Documentation/spi/ |
| A D | spi-lm70llp.rst | 45 D6 8 --> SCLK 3
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| A D | spi-summary.rst | 183 All spiB.* devices share one physical SPI bus segment, with SCLK,
631 SCLK ___ ___ ___ ___ ___ ___ ___ ___
670 SCLK ___ ___ ___ ___ ___ ___ ___ ___
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| /linux/Documentation/devicetree/bindings/iio/adc/ |
| A D | adi,ad4000.yaml | 143 # chain mode has lower SCLK max rate
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| A D | adi,ad7944.yaml | 162 # chain mode has lower SCLK max rate and doesn't work when TURBO is enabled
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| /linux/drivers/scsi/sym53c8xx_2/ |
| A D | sym_defs.h | 268 #define SCLK 0x80 /* Use the PCI clock as SCSI clock */ macro
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| /linux/Documentation/input/devices/ |
| A D | amijoy.rst | 102 the rising edge of SCLK. MLD output is used to parallel load
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| /linux/arch/arm/boot/dts/marvell/ |
| A D | armada-385-turris-omnia.dts | 587 /* MISO, MOSI, SCLK and CS2 are routed to pin header CN11 */
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| /linux/drivers/scsi/ |
| A D | ncr53c8xx.h | 791 #define SCLK 0x80 /* Use the PCI clock as SCSI clock */ macro
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu12/ |
| A D | renoir_ppt.c | 117 CLK_MAP(SCLK, CLOCK_GFXCLK),
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| A D | aldebaran_ppt.c | 159 CLK_MAP(SCLK, PPCLK_GFXCLK),
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| A D | smu_v13_0_7_ppt.c | 148 CLK_MAP(SCLK, PPCLK_GFXCLK),
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu14/ |
| A D | smu_v14_0_2_ppt.c | 142 CLK_MAP(SCLK, PPCLK_GFXCLK),
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