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Searched refs:SF (Results 1 – 25 of 76) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/optc/dcn401/
A Ddcn401_optc.h12 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
13 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
14 SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
26 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
32 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
39 SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
43 SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
75 SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
99 SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
100 SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn32/
A Ddcn32_optc.h47 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
53 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
60 SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
64 SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
96 SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
120 SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
121 SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
122 SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
134 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
136 SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_mmhubbub.h230 SF(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\
282 SF(MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\
289 SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_MODE, mask_sh),\
296 SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ, mask_sh),\
304 SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_MODE, mask_sh),\
311 SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ, mask_sh),\
319 SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_MODE, mask_sh),\
326 SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ, mask_sh),\
334 SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_MODE, mask_sh),\
341 SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_TMZ, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn30/
A Ddcn30_optc.h132 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
138 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
145 SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
149 SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
183 SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
212 SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
213 SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
214 SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
226 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
232 SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn31/
A Ddcn31_optc.h120 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
126 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
133 SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
137 SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
169 SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
192 SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
193 SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
194 SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
206 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
208 SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn314/
A Ddcn314_optc.h119 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
125 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
132 SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
136 SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
168 SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
191 SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
192 SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
193 SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
205 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
207 SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/
A Ddcn32_mmhubbub.h97 SF(MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\
99 SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_ACTIVE, mask_sh),\
103 SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_MODE, mask_sh),\
110 SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ, mask_sh),\
117 SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_MODE, mask_sh),\
124 SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ, mask_sh),\
131 SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_MODE, mask_sh),\
138 SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ, mask_sh),\
145 SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_MODE, mask_sh),\
152 SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_TMZ, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/
A Ddcn20_mmhubbub.h97 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\
107 SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\
114 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_MODE, mask_sh),\
117 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_FIELD, mask_sh),\
126 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ, mask_sh),\
134 SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_MODE, mask_sh),\
146 SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ, mask_sh),\
154 SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_MODE, mask_sh),\
166 SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ, mask_sh),\
247 SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_SEL, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn30/
A Ddcn30_mpc.h429 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
434 SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
453 SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\
459 SF(MPC_RMU_CONTROL, MPC_RMU0_MUX, mask_sh), \
460 SF(MPC_RMU_CONTROL, MPC_RMU1_MUX, mask_sh), \
536 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
561 SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\
567 SF(MPC_RMU_CONTROL, MPC_RMU0_MUX, mask_sh), \
568 SF(MPC_RMU_CONTROL, MPC_RMU1_MUX, mask_sh), \
827 SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn35/
A Ddcn35_optc.h34 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_WINDOW_DB_EN, mask_sh),\
35 SF(OTG0_OTG_CRC1_DATA_RG, CRC1_R_CR, mask_sh),\
36 SF(OTG0_OTG_CRC1_DATA_RG, CRC1_G_Y, mask_sh),\
37 SF(OTG0_OTG_CRC1_DATA_B, CRC1_B_CB, mask_sh),\
38 SF(OTG0_OTG_CRC2_DATA_RG, CRC2_R_CR, mask_sh),\
39 SF(OTG0_OTG_CRC2_DATA_RG, CRC2_G_Y, mask_sh),\
40 SF(OTG0_OTG_CRC2_DATA_B, CRC2_B_CB, mask_sh),\
41 SF(OTG0_OTG_CRC3_DATA_RG, CRC3_R_CR, mask_sh),\
42 SF(OTG0_OTG_CRC3_DATA_RG, CRC3_G_Y, mask_sh),\
43 SF(OTG0_OTG_CRC3_DATA_B, CRC3_B_CB, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn32/
A Ddcn32_mpc.h180 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
181 SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\
182 SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
187 SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
188 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
189 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\
190 SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\
207 SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\
208 SF(MPC_DWB0_MUX, MPC_DWB0_MUX_STATUS, mask_sh),\
209 SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn10/
A Ddcn10_optc.h224 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
231 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
238 SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
278 SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
286 SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\
302 SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
303 SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
304 SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
317 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
319 SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_dwb.h47 #define SF(reg_name, field_name, post_fix)\ macro
85 SF(CNV0_WB_ENABLE, WB_ENABLE, mask_sh),\
89 SF(CNV0_WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
90 SF(CNV0_WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\
91 SF(CNV0_CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\
92 SF(CNV0_CNV_MODE, CNV_STEREO_TYPE, mask_sh),\
93 SF(CNV0_CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\
94 SF(CNV0_CNV_MODE, CNV_EYE_SELECTION, mask_sh),\
97 SF(CNV0_CNV_MODE, CNV_STEREO_SPLIT, mask_sh),\
98 SF(CNV0_CNV_MODE, CNV_NEW_CONTENT, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn201/
A Ddcn201_optc.h49 SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
51 SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
52 SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
53 SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
54 SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
58 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \
63 SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
65 SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
66 SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\
67 SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn20/
A Ddcn20_optc.h54 SF(OTG0_OTG_GLOBAL_CONTROL2, DIG_UPDATE_LOCATION, mask_sh),\
57 SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
59 SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
60 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \
64 SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DSC_MODE, mask_sh),\
67 SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh),\
71 SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\
73 SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
76 SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\
77 SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn20/
A Ddcn20_mpc.h138 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
139 SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\
140 SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
144 SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
145 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
146 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\
147 SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\
169 SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\
175 SF(MPCC_OGAM0_MPCC_OGAM_MODE, MPCC_OGAM_MODE, mask_sh),\
176 SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_audio.h44 #define SF(reg_name, field_name, post_fix)\ macro
50 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
54 SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\
55 SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\
56 SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh),\
57 SF(DCCG_AUDIO_DTO1_PHASE, DCCG_AUDIO_DTO1_PHASE, mask_sh),\
70 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
71 SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\
72 SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\
73 SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn401/
A Ddcn401_mpc.h71 SF(MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE, MPCC_MCM_FIRST_GAMUT_REMAP_MODE, mask_sh), \
73 SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A, MPCC_MCM_FIRST_GAMUT_REMAP_C11_A, mask_sh), \
74 SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A, MPCC_MCM_FIRST_GAMUT_REMAP_C12_A, mask_sh), \
75 SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A, MPCC_MCM_FIRST_GAMUT_REMAP_C13_A, mask_sh), \
76 SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A, MPCC_MCM_FIRST_GAMUT_REMAP_C14_A, mask_sh), \
77 SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A, MPCC_MCM_FIRST_GAMUT_REMAP_C21_A, mask_sh), \
86 SF(MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE, MPCC_MCM_SECOND_GAMUT_REMAP_MODE, mask_sh), \
100 SF(MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_SELECT, MPCC_MCM_3DLUT_FL_SEL, mask_sh), \
101 SF(MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS, MPCC_MCM_3DLUT_FL_DONE, mask_sh), \
102 SF(MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS, MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW, mask_sh), \
[all …]
/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn10/
A Ddcn10_mpc.h64 SF(MPCC0_MPCC_TOP_SEL, MPCC_TOP_SEL, mask_sh),\
65 SF(MPCC0_MPCC_BOT_SEL, MPCC_BOT_SEL, mask_sh),\
66 SF(MPCC0_MPCC_CONTROL, MPCC_MODE, mask_sh),\
72 SF(MPCC0_MPCC_STATUS, MPCC_IDLE, mask_sh),\
73 SF(MPCC0_MPCC_STATUS, MPCC_BUSY, mask_sh),\
74 SF(MPCC0_MPCC_OPP_ID, MPCC_OPP_ID, mask_sh),\
75 SF(MPCC0_MPCC_BG_G_Y, MPCC_BG_G_Y, mask_sh),\
76 SF(MPCC0_MPCC_BG_R_CR, MPCC_BG_R_CR, mask_sh),\
77 SF(MPCC0_MPCC_BG_B_CB, MPCC_BG_B_CB, mask_sh),\
78 SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_EN, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_vmid.h41 SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_DEPTH, mask_sh),\
42 SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE, mask_sh),\
43 SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\
44 SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\
45 …SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4, mask_sh)…
46 …SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32, mask_sh…
47 SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4, mask_sh),\
48 SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32, mask_sh)
/linux/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn35/
A Ddcn35_mmhubbub.h39 SF(MMHUBBUB_CLOCK_CNTL, MMHUBBUB_TEST_CLK_SEL, mask_sh), \
40 SF(MMHUBBUB_CLOCK_CNTL, DISPCLK_R_MMHUBBUB_GATE_DIS, mask_sh), \
41 SF(MMHUBBUB_CLOCK_CNTL, DISPCLK_G_WBIF0_GATE_DIS, mask_sh), \
42 SF(MMHUBBUB_CLOCK_CNTL, SOCCLK_G_WBIF0_GATE_DIS, mask_sh), \
43 SF(MMHUBBUB_CLOCK_CNTL, MMHUBBUB_FGCG_REP_DIS, mask_sh)
/linux/drivers/gpu/drm/amd/display/dc/dcn201/
A Ddcn201_mpc.h44 SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL, mask_sh),\
45 SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL_DISABLE, mask_sh),\
46 SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_MODE, mask_sh),\
47 SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT0, mask_sh),\
48 SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT1, mask_sh)
/linux/fs/reiserfs/
A Dprocfs.c50 #define SF( x ) ( r -> x ) macro
51 #define SFP( x ) SF( s_proc_info_data.x )
102 SF(s_mount_state) == REISERFS_VALID_FS ? in show_super()
118 SF(s_disk_reads), SF(s_disk_writes), SF(s_fix_nodes), in show_super()
119 SF(s_do_balance), SF(s_unneeded_left_neighbor), in show_super()
120 SF(s_good_search_by_key_reada), SF(s_bmaps), in show_super()
121 SF(s_bmaps_without_search), SF(s_direct2indirect), in show_super()
122 SF(s_indirect2direct), SFP(max_hash_collisions), SFP(breads), in show_super()
/linux/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/
A Dswitchdev.rst49 device, and by default all the SF auxiliary devices are disabled.
50 This will allow user to configure the SF before the SF have been fully probed,
55 - Create SF::
64 - Now, in order to fully probe the SF, use devlink reload::
164 configuration of the PCI VF/SF is supported through devlink eswitch port.
180 PCI devices/SF.
213 SF state setup
216 To use the SF, the user must activate the SF using the SF function state
219 - Get the state of the SF identified by its unique devlink port index::
274 safe to delete the SF port for graceful termination of the subfunction.
[all …]
A Dtracepoints.rst152 SF tracepoints:
154 - mlx5_sf_add: trace addition of the SF port::
161 - mlx5_sf_free: trace freeing of the SF port::
168 - mlx5_sf_activate: trace activation of the SF port::
175 - mlx5_sf_deactivate: trace deactivation of the SF port::
182 - mlx5_sf_hwc_alloc: trace allocating of the hardware SF context::
189 - mlx5_sf_hwc_free: trace freeing of the hardware SF context::
203 - mlx5_sf_update_state: trace state updates for SF contexts::
210 - mlx5_sf_vhca_event: trace SF vhca event and state::
217 - mlx5_sf_dev_add: trace SF device add event::
[all …]

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