Searched refs:SKL_DPLL0 (Results 1 – 2 of 2) sorted by relevance
939 (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | in skl_dpll0_update()940 DPLL_CTRL1_SSC(SKL_DPLL0) | in skl_dpll0_update()941 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != in skl_dpll0_update()942 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) in skl_dpll0_update()945 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { in skl_dpll0_update()946 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): in skl_dpll0_update()957 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); in skl_dpll0_update()1061 DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | in skl_dpll0_enable()1062 DPLL_CTRL1_SSC(SKL_DPLL0) | in skl_dpll0_enable()1063 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0), in skl_dpll0_enable()[all …]
386 #define SKL_DPLL0 0 macro
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