| /linux/arch/arm64/boot/dts/renesas/ |
| A D | r9a07g044c2-smarc.dts | 11 * DIP-Switch SW1 setting on SoM
13 * SW1-2 : SW_SD0_DEV_SEL (1: eMMC; 0: uSD)
14 * SW1-3 : SW_SCIF_CAN (1: CAN1; 0: SCIF1)
15 * SW1-4 : SW_RSPI_CAN (1: CAN1; 0: RSPI1)
16 * SW1-5 : SW_I2S0_I2S1 (1: I2S2 (HDMI audio); 0: I2S0)
17 * Please change below macros according to SW1 setting
40 * - Set DIP-Switch SW1-4 to Off position.
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| A D | r9a07g043u11-smarc.dts | 11 * DIP-Switch SW1 setting
13 * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC)
14 * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1)
15 * Please change below macros according to SW1 setting on the SoM
22 * - Set DIP-Switch SW1-3 to On position.
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| A D | rzg2l-smarc-som.dtsi | 12 /* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */
17 * SW1[2] should be at position 3/ON.
262 * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
265 * SW1[2] should be at position 2/OFF to enable 64 GB eMMC
266 * SW1[2] should be at position 3/ON to enable uSD card CN3
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| A D | rzg2lc-smarc-som.dtsi | 180 * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
183 * SW1[2] should be at OFF position to enable 64 GB eMMC
184 * SW1[2] should be at position ON to enable uSD card CN3
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| A D | rzg2l-smarc.dtsi | 164 * SW1 should be at position 2->3 so that SER0_CTS# line is activated
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| A D | rzg2lc-smarc.dtsi | 181 * SW1 should be at position 2->3 so that SER0_CTS# line is activated
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| /linux/arch/riscv/boot/dts/renesas/ |
| A D | r9a07g043f01-smarc.dts | 11 * DIP-Switch SW1 setting
13 * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC)
14 * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1)
15 * Please change below macros according to SW1 setting on the SoM
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| /linux/arch/arm/boot/dts/renesas/ |
| A D | r8a7779-marzen.dts | 66 label = "SW1-1";
73 label = "SW1-2";
89 label = "SW1-3";
95 label = "SW1-4";
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| A D | r8a7742-iwg21d-q7-dbcm-ca.dts | 238 * Set SW1 switch on camera board to 'OFF' as we are using 8bit mode
270 /* Set SW1 switch on the SOM to 'ON' */
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| A D | r7s72100-rskrza1.dts | 84 label = "SW1";
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| A D | sh73a0-kzm9g.dts | 143 label = "SW1";
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| /linux/Documentation/hid/ |
| A D | hid-alps.rst | 114 1 0 0 SW6 SW5 SW4 SW3 SW2 SW1
148 SW1-SW6:
164 Byte1 1 1 1 0 1 SW3 SW2 SW1
173 SW1-SW3:
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| /linux/Documentation/devicetree/bindings/regulator/ |
| A D | pv88060.txt | 11 BUCK1, LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7, SW1, SW2, SW3, SW4,
84 SW1 {
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| /linux/Documentation/networking/ |
| A D | arcnet-hardware.rst | 829 SW1 1-6: I/O Base Address Select
1063 SW1: DIP-Switches for Station Address
1573 SW1 1-6: Base I/O Address Select
1839 | |SW1| o|o |
1850 SW1 1-6 Base I/O Address Select
1995 SW1 1-5: Base Memory Address Select
2141 SW1 1-5 Base Memory Address Select
2867 SW1 1-5: Base Memory Address Select
3036 SW1 1-5: IRQ Select
3047 SW1: Timeouts, Interrupt and ROM
[all …]
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| /linux/drivers/regulator/ |
| A D | pcap-regulator.c | 131 VREG_INFO(SW1, PCAP_REG_SWCTRL, 1, 2, NA, NA),
228 VREG(VAUX4), VREG(VSIM), VREG(VSIM2), VREG(VVIB), VREG(SW1), VREG(SW2),
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| A D | cpcap-regulator.c | 330 CPCAP_REG(SW1, CPCAP_REG_S1C1, CPCAP_REG_ASSIGN2,
406 CPCAP_REG(SW1, CPCAP_REG_S1C1, CPCAP_REG_ASSIGN2,
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| A D | pv88060-regulator.c | 217 PV88060_SW(PV88060, SW1, 5000000),
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| A D | ltc3676.c | 225 LTC3676_LINEAR_REG(SW1, sw1, BUCK1, DVB1A),
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| A D | ltc3589.c | 254 LTC3589_LINEAR_REG(SW1, sw1, B1DTV1),
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| A D | mc13892-regulator.c | 267 MC13892_SW_DEFINE(SW1, sw1, SWITCHERS0, SWITCHERS0, mc13892_sw1),
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| /linux/include/linux/mfd/ |
| A D | ezx-pcap.h | 130 #define SW1 17 macro
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| /linux/arch/arm/boot/dts/nxp/imx/ |
| A D | imx53-qsrb.dts | 35 regulator-name = "SW1";
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| /linux/arch/arm/boot/dts/microchip/ |
| A D | at91-kizbox3-hs.dts | 72 label = "SW1";
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| /linux/Documentation/devicetree/bindings/mfd/ |
| A D | mc13xxx.txt | 86 sw1 : regulator SW1 (register 24, bit 0)
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| /linux/arch/arm64/boot/dts/amlogic/ |
| A D | meson-g12b-odroid-n2.dtsi | 291 * The SW1 slide should also be set to the correct position.
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