Searched refs:TCS (Results 1 – 6 of 6) sorted by relevance
43 # RBX contains the base address for TCS, which is the first address44 # inside the enclave for TCS #1 and one page into the enclave for45 # TCS #2. First make it relative by substracting __encl_base and53 # Entry point for dynamically created TCS page expected to follow87 # Stack of TCS #191 # Stack of TCS #2
15 resources can be written to the Trigger Command Set (TCS) registers and16 using a (addr, val) pair and triggered. Messages in the TCS are then sent in25 A TCS may be triggered from Linux or triggered by the F/W after all the CPUs73 TCS type::79 - description: Number of TCS81 The tuple defining the configuration of TCS. Must have two cells which82 describe each TCS type. The order of the TCS must match the hardware88 The offset of the TCS blocks.133 // For a TCS whose RSC base address is 0x179C0000 and is at a DRV id of139 // TCS-OFFSET: 0xD00[all …]
30 The AMC TCS is triggered immediately when icc_set_bw() is called. The
131 TCS = TSNMHD + 0x0204, enumerator
58 **Thread Control Structure (TCS)**
1372 Now 'perf inject' can be used to determine the VMX TCS Offset. Note, Intel PT TSC packets are
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