Searched refs:TILE_SPLIT (Results 1 – 16 of 16) sorted by relevance
435 TILE_SPLIT(split_equal_to_row_size); in gfx_v6_0_tiling_mode_table_init()525 TILE_SPLIT(split_equal_to_row_size); in gfx_v6_0_tiling_mode_table_init()536 TILE_SPLIT(split_equal_to_row_size); in gfx_v6_0_tiling_mode_table_init()544 TILE_SPLIT(split_equal_to_row_size); in gfx_v6_0_tiling_mode_table_init()782 TILE_SPLIT(split_equal_to_row_size); in gfx_v6_0_tiling_mode_table_init()790 TILE_SPLIT(split_equal_to_row_size); in gfx_v6_0_tiling_mode_table_init()865 TILE_SPLIT(split_equal_to_row_size); in gfx_v6_0_tiling_mode_table_init()955 TILE_SPLIT(split_equal_to_row_size); in gfx_v6_0_tiling_mode_table_init()966 TILE_SPLIT(split_equal_to_row_size); in gfx_v6_0_tiling_mode_table_init()974 TILE_SPLIT(split_equal_to_row_size); in gfx_v6_0_tiling_mode_table_init()[all …]
2090 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in gfx_v8_0_tiling_mode_table_init()2106 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | in gfx_v8_0_tiling_mode_table_init()2110 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | in gfx_v8_0_tiling_mode_table_init()2114 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | in gfx_v8_0_tiling_mode_table_init()2262 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in gfx_v8_0_tiling_mode_table_init()2278 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | in gfx_v8_0_tiling_mode_table_init()2282 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | in gfx_v8_0_tiling_mode_table_init()2286 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | in gfx_v8_0_tiling_mode_table_init()2290 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | in gfx_v8_0_tiling_mode_table_init()2451 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in gfx_v8_0_tiling_mode_table_init()[all …]
1018 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in gfx_v7_0_tiling_mode_table_init()1035 TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1042 TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1185 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in gfx_v7_0_tiling_mode_table_init()1202 TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1206 TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1210 TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1214 TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1371 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in gfx_v7_0_tiling_mode_table_init()1388 TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()[all …]
191 # define TILE_SPLIT(x) ((x) << 11) macro
1022 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) in amdgpu_bo_set_tiling_flags()
1195 # define TILE_SPLIT(x) ((x) << 11) macro
1962 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v6_0_crtc_do_set_base()
1931 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v8_0_crtc_do_set_base()
1992 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v10_0_crtc_do_set_base()
2042 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v11_0_crtc_do_set_base()
2499 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in si_tiling_mode_table_init()2535 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in si_tiling_mode_table_init()2544 TILE_SPLIT(split_equal_to_row_size) | in si_tiling_mode_table_init()2553 TILE_SPLIT(split_equal_to_row_size) | in si_tiling_mode_table_init()2562 TILE_SPLIT(split_equal_to_row_size) | in si_tiling_mode_table_init()2571 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in si_tiling_mode_table_init()2652 TILE_SPLIT(split_equal_to_row_size) | in si_tiling_mode_table_init()2759 TILE_SPLIT(split_equal_to_row_size) | in si_tiling_mode_table_init()2768 TILE_SPLIT(split_equal_to_row_size) | in si_tiling_mode_table_init()2777 TILE_SPLIT(split_equal_to_row_size) | in si_tiling_mode_table_init()[all …]
2360 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B)); in cik_tiling_mode_table_init()2376 TILE_SPLIT(split_equal_to_row_size)); in cik_tiling_mode_table_init()2387 TILE_SPLIT(split_equal_to_row_size)); in cik_tiling_mode_table_init()2519 TILE_SPLIT(split_equal_to_row_size)); in cik_tiling_mode_table_init()2530 TILE_SPLIT(split_equal_to_row_size)); in cik_tiling_mode_table_init()2663 TILE_SPLIT(split_equal_to_row_size)); in cik_tiling_mode_table_init()2674 TILE_SPLIT(split_equal_to_row_size)); in cik_tiling_mode_table_init()2743 TILE_SPLIT(split_equal_to_row_size)); in cik_tiling_mode_table_init()2754 TILE_SPLIT(split_equal_to_row_size)); in cik_tiling_mode_table_init()2887 TILE_SPLIT(split_equal_to_row_size)); in cik_tiling_mode_table_init()[all …]
1198 # define TILE_SPLIT(x) ((x) << 11) macro
1240 # define TILE_SPLIT(x) ((x) << 11) macro
189 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
1730 typedef enum TILE_SPLIT { enum1738 } TILE_SPLIT; typedef
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