Searched refs:VCLK (Results 1 – 20 of 20) sorted by relevance
| /linux/drivers/video/fbdev/sis/ |
| A D | init.c | 2313 VCLK = SiS_Pr->CSRClock; in SiS_SetCRT1FIFO_300()
2440 VCLK = SiS_Pr->CSRClock; in SiS_SetCRT1FIFO_630()
2580 VCLK = SiS_Pr->CSRClock; in SiS_SetVCLKState()
2589 if(VCLK > 150) data |= 0x80; in SiS_SetVCLKState()
2593 if(VCLK >= 150) data |= 0x08; in SiS_SetVCLKState()
2598 if(VCLK >= 166) data |= 0x0c; in SiS_SetVCLKState()
2601 if(VCLK >= 166) { in SiS_SetVCLKState()
2607 if(VCLK >= 200) data |= 0x0c; in SiS_SetVCLKState()
2612 if(VCLK < 200) data |= 0x10; in SiS_SetVCLKState()
2626 if(VCLK >= 260) data = 0x00; in SiS_SetVCLKState()
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| A D | init301.c | 5336 unsigned short VCLK = 0, MCLK, colorth = 0, data2 = 0; in SiS_SetCRT2FIFO_300() local
5356 VCLK = SiS_Pr->SiS_VCLKData[index].CLOCK; in SiS_SetCRT2FIFO_300()
5368 VCLK = SiS_Pr->CSRClock_CRT1; in SiS_SetCRT2FIFO_300()
5389 data2 = temp - ((colorth * VCLK) / MCLK); in SiS_SetCRT2FIFO_300()
5446 VCLK = SiS_Pr->SiS_VCLKData[index].CLOCK; in SiS_SetCRT2FIFO_300()
5451 VCLK = ROMAddr[0x229] | (ROMAddr[0x22a] << 8); in SiS_SetCRT2FIFO_300()
5460 VCLK = SiS_Pr->CSRClock; in SiS_SetCRT2FIFO_300()
5468 data = data * VCLK * colorth; in SiS_SetCRT2FIFO_300()
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| /linux/Documentation/devicetree/bindings/display/ |
| A D | amlogic,meson-vpu.yaml | 20 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
53 The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock
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| /linux/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| A D | power_state.h | 144 uint32_t VCLK; member
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| /linux/Documentation/gpu/ |
| A D | meson.rst | 19 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
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| /linux/Documentation/devicetree/bindings/display/samsung/ |
| A D | samsung,fimd.yaml | 46 VCLK(internal) __|??????|_____|??????|_____|??????|_____|??????|_____|??
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| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| A D | processpptables.c | 756 ps->uvd_clocks.VCLK = le32_to_cpu(pnon_clock_info->ulVCLK); in init_non_clock_fields()
759 ps->uvd_clocks.VCLK = 0; in init_non_clock_fields()
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| A D | smu10_hwmgr.c | 933 smu10_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK; in smu10_dpm_get_pp_table_entry()
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| A D | smu7_hwmgr.c | 3636 power_state->uvd_clocks.VCLK = 0; in smu7_get_pp_table_entry_callback_func_v1()
3729 ps->uvd_clks.vclk = state->uvd_clocks.VCLK; in smu7_get_pp_table_entry_v1()
3877 ps->uvd_clks.vclk = state->uvd_clocks.VCLK; in smu7_get_pp_table_entry_v0()
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| A D | smu8_hwmgr.c | 1438 smu8_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK; in smu8_dpm_get_pp_table_entry()
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| A D | vega10_hwmgr.c | 3184 power_state->uvd_clocks.VCLK = 0; in vega10_get_pp_table_entry_callback_func()
3264 vega10_ps->uvd_clks.vclk = state->uvd_clocks.VCLK; in vega10_get_pp_table_entry()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu12/ |
| A D | renoir_ppt.c | 121 CLK_MAP(VCLK, CLOCK_VCLK),
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| A D | aldebaran_ppt.c | 165 CLK_MAP(VCLK, PPCLK_VCLK),
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| A D | smu_v13_0_7_ppt.c | 153 CLK_MAP(VCLK, PPCLK_VCLK_0),
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| A D | smu_v13_0_0_ppt.c | 182 CLK_MAP(VCLK, PPCLK_VCLK_0),
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| A D | smu_v13_0_6_ppt.c | 188 CLK_MAP(VCLK, PPCLK_VCLK),
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu14/ |
| A D | smu_v14_0_2_ppt.c | 147 CLK_MAP(VCLK, PPCLK_VCLK_0),
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| A D | arcturus_ppt.c | 172 CLK_MAP(VCLK, PPCLK_VCLK),
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| A D | navi10_ppt.c | 157 CLK_MAP(VCLK, PPCLK_VCLK),
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| A D | sienna_cichlid_ppt.c | 173 CLK_MAP(VCLK, PPCLK_VCLK_0),
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