Searched refs:VLV_DISPLAY_BASE (Results 1 – 11 of 11) sorted by relevance
235 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)236 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)272 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)273 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)280 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)281 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)296 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)297 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)324 #define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)340 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0)[all …]
272 #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)273 #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)274 #define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908)276 #define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910)277 #define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000)283 #define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000)289 #define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00)298 #define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910)299 #define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000)300 #define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000)[all …]
41 #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)42 #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)44 #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)45 #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)47 #define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0)55 #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)56 #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)152 #define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000)155 #define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38)161 #define VLV_AUD_PORT_EN_DBG(port) _MMIO_BASE_PORT3(VLV_DISPLAY_BASE, (port) - PORT_B, \
11 #define _VLV_BLC_PWM_CTL2_A (VLV_DISPLAY_BASE + 0x61250)12 #define _VLV_BLC_PWM_CTL2_B (VLV_DISPLAY_BASE + 0x61350)15 #define _VLV_BLC_PWM_CTL_A (VLV_DISPLAY_BASE + 0x61254)16 #define _VLV_BLC_PWM_CTL_B (VLV_DISPLAY_BASE + 0x61354)19 #define _VLV_BLC_HIST_CTL_A (VLV_DISPLAY_BASE + 0x61260)20 #define _VLV_BLC_HIST_CTL_B (VLV_DISPLAY_BASE + 0x61360)
28 #define VLV_DP_AUX_CH_CTL(aux_ch) _MMIO(VLV_DISPLAY_BASE + \82 #define VLV_DP_AUX_CH_DATA(aux_ch, i) _MMIO(VLV_DISPLAY_BASE + _PORT(aux_ch, _DPA_AUX_CH_DATA1, \
14 #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
13 #define VLV_DISPLAY_BASE 0x180000 macro
11 #define VLV_MIPI_BASE VLV_DISPLAY_BASE
471 .mmio_offset = VLV_DISPLAY_BASE,574 .mmio_offset = VLV_DISPLAY_BASE,
873 i915->display.gmbus.mmio_base = VLV_DISPLAY_BASE; in intel_gmbus_setup()
192 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)392 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)429 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)430 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)431 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)432 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)433 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)434 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)1879 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)1886 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)[all …]
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