| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn20/ |
| A D | dcn20_hubp.h | 116 HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh) 204 type VMID
|
| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn21/ |
| A D | dcn21_hubp.h | 91 HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\
|
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_amdkfd_gfx_v7.c | 51 uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue); in lock_srbm() 561 return REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in read_vmid_from_vmfault_reg()
|
| A D | vid.h | 72 #define VMID(x) ((x) << 4) macro
|
| A D | cikd.h | 59 #define VMID(x) ((x) << 4) macro
|
| A D | gfx_v11_0.c | 2333 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_me_cache() 2377 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_pfp_cache() 2452 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_pfp_cache_rs64() 2574 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_me_cache_rs64() 2692 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_mec_cache_rs64() 2698 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_mec_cache_rs64() 3062 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64() 3280 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_cp_gfx_load_me_microcode_rs64() 3922 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); in gfx_v11_0_gfx_mqd_init() 3929 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); in gfx_v11_0_gfx_mqd_init() [all …]
|
| A D | amdgpu_amdkfd_gfx_v10.c | 907 VMID, in kgd_gfx_v10_set_address_watch() 921 VMID, in kgd_gfx_v10_set_address_watch()
|
| A D | mes_v12_0.c | 1036 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in mes_v12_0_mqd_init() 1119 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); in mes_v12_0_queue_init_register() 1134 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); in mes_v12_0_queue_init_register()
|
| A D | soc24.c | 108 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); in soc24_grbm_select()
|
| A D | mes_v11_0.c | 1070 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in mes_v11_0_mqd_init() 1146 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); in mes_v11_0_queue_init_register() 1161 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); in mes_v11_0_queue_init_register()
|
| A D | umsch_mm_v4_0.c | 84 data = REG_SET_FIELD(data, VCN_MES_IC_BASE_CNTL, VMID, 0); in umsch_mm_v4_0_load_microcode()
|
| A D | amdgpu_amdkfd_gfx_v8.c | 45 uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue); in lock_srbm()
|
| A D | gmc_v7_0.c | 759 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in gmc_v7_0_vm_decode_fault() 1288 VMID); in gmc_v7_0_process_interrupt()
|
| A D | gfx_v12_0.c | 2275 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64() 2329 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64() 2419 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); in gfx_v12_0_cp_gfx_load_me_microcode_rs64() 2474 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); in gfx_v12_0_cp_gfx_load_me_microcode_rs64() 2736 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); in gfx_v12_0_cp_compute_load_microcode_rs64() 2742 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); in gfx_v12_0_cp_compute_load_microcode_rs64() 2855 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); in gfx_v12_0_gfx_mqd_init() 2862 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); in gfx_v12_0_gfx_mqd_init() 3047 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in gfx_v12_0_compute_mqd_init()
|
| A D | gmc_v8_0.c | 991 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in gmc_v8_0_vm_decode_fault() 1469 VMID); in gmc_v8_0_process_interrupt()
|
| /linux/Documentation/trace/coresight/ |
| A D | coresight-etm4x-reference.rst | 461 Automatically clears masked bytes to 0 in VMID value registers. 466 Where mN represents a byte mask value for VMID comparator N. 468 VMID comparators. 475 Number of VMID comparators
|
| A D | coresight-cpu-debug.rst | 188 …esight-cpu-debug 850000.debug: EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0) 193 …esight-cpu-debug 852000.debug: EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0)
|
| /linux/Documentation/devicetree/bindings/sound/ |
| A D | nuvoton,nau8821.yaml | 66 description: VMID Tie-off impedance select.
|
| /linux/drivers/gpu/drm/radeon/ |
| A D | cik_sdma.c | 961 radeon_ring_write(ring, VMID(vm_id)); in cik_dma_vm_flush() 981 radeon_ring_write(ring, VMID(0)); in cik_dma_vm_flush()
|
| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn31/ |
| A D | dcn31_hubp.h | 224 HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\
|
| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn30/ |
| A D | dcn30_hubp.c | 82 VMID, address->vmid); in hubp3_program_surface_flip_and_addr()
|
| A D | dcn30_hubp.h | 239 HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\
|
| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn401/ |
| A D | dcn401_hubp.h | 211 HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\
|
| /linux/Documentation/ABI/testing/ |
| A D | sysfs-bus-coresight-devices-etm4x | 55 Description: (Read) Indicates the number of VMID comparators that are available 449 VMID, context ID and instruction address in the trace unit
|
| /linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| A D | smu8_smumgr.c | 200 tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); in smu8_load_mec_firmware()
|