| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| A D | dcn316_clk_mgr.c | 357 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn316_build_watermark_ranges()
358 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn316_build_watermark_ranges()
362 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; in dcn316_build_watermark_ranges()
365 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = in dcn316_build_watermark_ranges()
368 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = in dcn316_build_watermark_ranges()
373 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn316_build_watermark_ranges()
374 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn316_build_watermark_ranges()
385 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0; in dcn316_build_watermark_ranges()
386 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in dcn316_build_watermark_ranges()
387 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF; in dcn316_build_watermark_ranges()
[all …]
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| A D | dcn316_smu.h | 56 WM_DCFCLK, enumerator
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| A D | vg_clk_mgr.c | 400 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in vg_build_watermark_ranges()
401 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in vg_build_watermark_ranges()
405 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; in vg_build_watermark_ranges()
408 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = in vg_build_watermark_ranges()
411 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = in vg_build_watermark_ranges()
416 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in vg_build_watermark_ranges()
417 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in vg_build_watermark_ranges()
428 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0; in vg_build_watermark_ranges()
429 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in vg_build_watermark_ranges()
430 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF; in vg_build_watermark_ranges()
[all …]
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| A D | dcn301_smu.h | 71 WM_DCFCLK, enumerator
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| A D | dcn31_clk_mgr.c | 435 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn31_build_watermark_ranges()
436 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn31_build_watermark_ranges()
440 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; in dcn31_build_watermark_ranges()
443 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = in dcn31_build_watermark_ranges()
446 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = in dcn31_build_watermark_ranges()
451 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn31_build_watermark_ranges()
452 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn31_build_watermark_ranges()
463 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0; in dcn31_build_watermark_ranges()
464 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in dcn31_build_watermark_ranges()
465 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF; in dcn31_build_watermark_ranges()
[all …]
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| A D | dcn31_smu.h | 68 WM_DCFCLK, enumerator
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| A D | dcn315_clk_mgr.c | 395 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn315_build_watermark_ranges()
396 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn315_build_watermark_ranges()
400 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; in dcn315_build_watermark_ranges()
403 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = in dcn315_build_watermark_ranges()
406 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = in dcn315_build_watermark_ranges()
411 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn315_build_watermark_ranges()
412 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn315_build_watermark_ranges()
423 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0; in dcn315_build_watermark_ranges()
424 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in dcn315_build_watermark_ranges()
425 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF; in dcn315_build_watermark_ranges()
[all …]
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| A D | dcn315_smu.h | 57 WM_DCFCLK, enumerator
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| A D | dcn314_clk_mgr.c | 500 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn314_build_watermark_ranges()
501 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn314_build_watermark_ranges()
505 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; in dcn314_build_watermark_ranges()
508 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = in dcn314_build_watermark_ranges()
511 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = in dcn314_build_watermark_ranges()
516 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn314_build_watermark_ranges()
517 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn314_build_watermark_ranges()
528 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0; in dcn314_build_watermark_ranges()
529 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in dcn314_build_watermark_ranges()
530 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF; in dcn314_build_watermark_ranges()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| A D | dcn35_clk_mgr.c | 656 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn35_build_watermark_ranges()
657 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn35_build_watermark_ranges()
661 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; in dcn35_build_watermark_ranges()
664 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = in dcn35_build_watermark_ranges()
667 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = in dcn35_build_watermark_ranges()
672 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn35_build_watermark_ranges()
673 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn35_build_watermark_ranges()
684 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0; in dcn35_build_watermark_ranges()
685 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in dcn35_build_watermark_ranges()
686 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF; in dcn35_build_watermark_ranges()
[all …]
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| A D | dcn35_smu.h | 65 WM_DCFCLK, enumerator
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| /linux/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| A D | smu10_driver_if.h | 65 WM_DCFCLK, enumerator
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| /linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
| A D | smu13_driver_if_v13_0_5.h | 67 WM_DCFCLK, enumerator
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| A D | smu13_driver_if_yellow_carp.h | 66 WM_DCFCLK, enumerator
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| A D | smu12_driver_if.h | 67 WM_DCFCLK, enumerator
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| A D | smu11_driver_if_vangogh.h | 66 WM_DCFCLK, enumerator
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| A D | smu13_driver_if_v13_0_4.h | 67 WM_DCFCLK, enumerator
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| A D | smu14_driver_if_v14_0_0.h | 62 WM_DCFCLK, enumerator
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| A D | smu_v13_0_5_ppt.c | 422 table->WatermarkRow[WM_DCFCLK][i].MinClock = in smu_v13_0_5_set_watermarks_table()
424 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in smu_v13_0_5_set_watermarks_table()
426 table->WatermarkRow[WM_DCFCLK][i].MinMclk = in smu_v13_0_5_set_watermarks_table()
428 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = in smu_v13_0_5_set_watermarks_table()
431 table->WatermarkRow[WM_DCFCLK][i].WmSetting = in smu_v13_0_5_set_watermarks_table()
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| A D | smu_v13_0_4_ppt.c | 678 table->WatermarkRow[WM_DCFCLK][i].MinClock = in smu_v13_0_4_set_watermarks_table()
680 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in smu_v13_0_4_set_watermarks_table()
682 table->WatermarkRow[WM_DCFCLK][i].MinMclk = in smu_v13_0_4_set_watermarks_table()
684 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = in smu_v13_0_4_set_watermarks_table()
687 table->WatermarkRow[WM_DCFCLK][i].WmSetting = in smu_v13_0_4_set_watermarks_table()
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| A D | yellow_carp_ppt.c | 513 table->WatermarkRow[WM_DCFCLK][i].MinClock = in yellow_carp_set_watermarks_table()
515 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in yellow_carp_set_watermarks_table()
517 table->WatermarkRow[WM_DCFCLK][i].MinMclk = in yellow_carp_set_watermarks_table()
519 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = in yellow_carp_set_watermarks_table()
522 table->WatermarkRow[WM_DCFCLK][i].WmSetting = in yellow_carp_set_watermarks_table()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu12/ |
| A D | renoir_ppt.c | 1094 table->WatermarkRow[WM_DCFCLK][i].MinClock = in renoir_set_watermarks_table()
1096 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in renoir_set_watermarks_table()
1098 table->WatermarkRow[WM_DCFCLK][i].MinMclk = in renoir_set_watermarks_table()
1100 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = in renoir_set_watermarks_table()
1103 table->WatermarkRow[WM_DCFCLK][i].WmSetting = in renoir_set_watermarks_table()
1105 table->WatermarkRow[WM_DCFCLK][i].WmType = in renoir_set_watermarks_table()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu14/ |
| A D | smu_v14_0_0_ppt.c | 497 table->WatermarkRow[WM_DCFCLK][i].MinClock = in smu_v14_0_0_set_watermarks_table()
499 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in smu_v14_0_0_set_watermarks_table()
501 table->WatermarkRow[WM_DCFCLK][i].MinMclk = in smu_v14_0_0_set_watermarks_table()
503 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = in smu_v14_0_0_set_watermarks_table()
506 table->WatermarkRow[WM_DCFCLK][i].WmSetting = in smu_v14_0_0_set_watermarks_table()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| A D | vangogh_ppt.c | 1625 table->WatermarkRow[WM_DCFCLK][i].MinClock = in vangogh_set_watermarks_table()
1627 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in vangogh_set_watermarks_table()
1629 table->WatermarkRow[WM_DCFCLK][i].MinMclk = in vangogh_set_watermarks_table()
1631 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = in vangogh_set_watermarks_table()
1634 table->WatermarkRow[WM_DCFCLK][i].WmSetting = in vangogh_set_watermarks_table()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| A D | smu10_hwmgr.c | 1373 table->WatermarkRow[WM_DCFCLK][i].WmType = (uint8_t)0; in smu10_set_watermarks_for_clocks_ranges()
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