| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | hdp_v4_0.c | 149 WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1); in hdp_v4_0_init_registers() 159 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1); in hdp_v4_0_init_registers() 162 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, READ_BUFFER_WATERMARK, 2); in hdp_v4_0_init_registers()
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| A D | df_v1_7.c | 117 WREG32_FIELD15(DF, 0, DF_CS_AON0_CoherentSlaveModeCtrlA0, in df_v1_7_enable_ecc_force_par_wr_rmw()
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| A D | nbio_v7_4.c | 212 WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0); in nbio_v7_4_enable_doorbell_aperture() 649 WREG32_FIELD15(NBIO, 0, BIF_DOORBELL_INT_CNTL_ALDE, in nbio_v7_4_enable_doorbell_interrupt() 652 WREG32_FIELD15(NBIO, 0, BIF_DOORBELL_INT_CNTL, in nbio_v7_4_enable_doorbell_interrupt()
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| A D | gfxhub_v1_0.c | 137 WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2, in gfxhub_v1_0_init_system_aperture_regs() 366 WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v1_0_gart_disable()
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| A D | gfxhub_v2_0.c | 181 WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, in gfxhub_v2_0_init_system_aperture_regs() 381 WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v2_0_gart_disable()
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| A D | vega20_ih.c | 343 WREG32_FIELD15(OSSSYS, 0, IH_RETRY_INT_CAM_CNTL_ALDEBARAN, in vega20_ih_irq_init() 346 WREG32_FIELD15(OSSSYS, 0, IH_RETRY_INT_CAM_CNTL, ENABLE, 1); in vega20_ih_irq_init()
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| A D | nbio_v7_0.c | 108 WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0); in nbio_v7_0_enable_doorbell_aperture()
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| A D | gfx_v9_0.c | 2864 WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1); in gfx_v9_0_enable_save_restore_machine() 3063 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0); in gfx_v9_0_rlc_stop() 3082 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v9_0_rlc_start() 3611 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v9_0_kiq_init_register() 4024 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v9_0_hw_fini() 5947 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_gfx_eop_interrupt_state() 6045 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_priv_reg_fault_state() 6081 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_bad_op_fault_state() 6114 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_priv_inst_fault_state() 6140 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_cp_ecc_error_state() [all …]
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| A D | gfxhub_v2_1.c | 185 WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, in gfxhub_v2_1_init_system_aperture_regs() 407 WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v2_1_gart_disable()
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| A D | nbio_v6_1.c | 110 WREG32_FIELD15(NBIO, 0, RCC_PF_0_0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0); in nbio_v6_1_enable_doorbell_aperture()
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| A D | soc15_common.h | 50 #define WREG32_FIELD15(ip, idx, reg, field, val) \ macro
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| A D | nbio_v2_3.c | 159 WREG32_FIELD15(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, in nbio_v2_3_enable_doorbell_aperture()
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| A D | amdgpu_amdkfd_gfx_v10_3.c | 513 WREG32_FIELD15(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0); in hqd_destroy_v10_3()
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| A D | amdgpu_amdkfd_gfx_v10.c | 534 WREG32_FIELD15(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0); in kgd_hqd_destroy()
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| A D | gmc_v9_0.c | 2343 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); in gmc_v9_0_hw_init() 2345 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); in gmc_v9_0_hw_init()
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| A D | gfx_v10_0.c | 5191 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); in gfx_v10_0_constants_init() 5324 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v10_0_rlc_reset() 5326 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v10_0_rlc_reset() 5361 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v10_0_rlc_start() 6896 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v10_0_kiq_init_register() 6989 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); in gfx_v10_0_kiq_init_register() 10097 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1); in gfx_v10_3_program_pbb_mode()
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