| /linux/drivers/gpu/drm/radeon/ |
| A D | trinity_smc.c | 66 WREG32_SMC(SMU_SCRATCH0, 1); in trinity_dpm_config() 68 WREG32_SMC(SMU_SCRATCH0, 0); in trinity_dpm_config() 75 WREG32_SMC(SMU_SCRATCH0, n); in trinity_dpm_force_state() 82 WREG32_SMC(SMU_SCRATCH0, n); in trinity_dpm_n_levels_disabled()
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| A D | trinity_dpm.c | 335 WREG32_SMC(GFX_POWER_GATING_CNTL, value); in trinity_gfx_powergating_initialize() 477 WREG32_SMC(PM_I_CNTL_1, value); in trinity_gfx_dynamic_mgpg_enable() 482 WREG32_SMC(SMU_S_PG_CNTL, value); in trinity_gfx_dynamic_mgpg_enable() 486 WREG32_SMC(SMU_S_PG_CNTL, value); in trinity_gfx_dynamic_mgpg_enable() 490 WREG32_SMC(PM_I_CNTL_1, value); in trinity_gfx_dynamic_mgpg_enable() 712 WREG32_SMC(SMU_SCLK_DPM_CNTL, value); in trinity_start_dpm() 845 WREG32_SMC(SMU_UVD_DPM_CNTL, val); in trinity_setup_uvd_dpm_interval() 965 WREG32_SMC(SMU_SCLK_DPM_TTT, value); in trinity_program_ttt() 974 WREG32_SMC(SMU_SCLK_DPM_TT_CNTL, value); in trinity_enable_att() 992 WREG32_SMC(PM_I_CNTL_1, value); in trinity_program_sclk_dpm() [all …]
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| A D | ci_smc.c | 119 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in ci_start_smc() 127 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in ci_reset_smc() 143 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in ci_stop_smc_clock() 152 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in ci_start_smc_clock()
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| A D | si_smc.c | 119 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in si_start_smc() 133 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in si_reset_smc() 149 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in si_stop_smc_clock() 158 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in si_start_smc_clock()
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| A D | ci_dpm.c | 920 WREG32_SMC(CG_FDO_CTRL2, tmp); in ci_fan_ctrl_set_static_mode() 924 WREG32_SMC(CG_FDO_CTRL2, tmp); in ci_fan_ctrl_set_static_mode() 1098 WREG32_SMC(CG_FDO_CTRL0, tmp); in ci_fan_ctrl_set_fan_speed_percent() 2041 WREG32_SMC(CG_FTV_0, 0); in ci_clear_vc() 2042 WREG32_SMC(CG_FTV_1, 0); in ci_clear_vc() 2043 WREG32_SMC(CG_FTV_2, 0); in ci_clear_vc() 2044 WREG32_SMC(CG_FTV_3, 0); in ci_clear_vc() 2045 WREG32_SMC(CG_FTV_4, 0); in ci_clear_vc() 2046 WREG32_SMC(CG_FTV_5, 0); in ci_clear_vc() 2047 WREG32_SMC(CG_FTV_6, 0); in ci_clear_vc() [all …]
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| A D | kv_dpm.c | 190 WREG32_SMC(config_regs->offset, data); in kv_program_pt_config_registers() 367 WREG32_SMC(CG_FTV_0, 0x3FFFC100); in kv_program_vc() 372 WREG32_SMC(CG_FTV_0, 0); in kv_clear_vc() 490 WREG32_SMC(GENERAL_PWRMGT, tmp); in kv_start_dpm() 507 WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl); in kv_start_am() 516 WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl); in kv_reset_am() 1023 WREG32_SMC(CG_THERMAL_INT_CTRL, thermal_int); in kv_enable_thermal_int() 2244 WREG32_SMC(NB_DPM_CONFIG_1, nbdpmconfig1); in kv_program_nbps_index_settings() 2268 WREG32_SMC(CG_THERMAL_INT_CTRL, tmp); in kv_set_thermal_temperature_range()
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| A D | cik.c | 9422 WREG32_SMC(cntl_reg, tmp); in cik_set_uvd_clock() 9469 WREG32_SMC(CG_ECLK_CNTL, tmp); in cik_set_vce_clocks() 9742 WREG32_SMC(THM_CLK_CNTL, data); in cik_program_aspm() 9748 WREG32_SMC(MISC_CLK_CTRL, data); in cik_program_aspm() 9753 WREG32_SMC(CG_CLKPIN_CNTL, data); in cik_program_aspm() 9758 WREG32_SMC(CG_CLKPIN_CNTL_2, data); in cik_program_aspm() 9764 WREG32_SMC(MPLL_BYPASSCLK_SEL, data); in cik_program_aspm()
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| A D | si.c | 5446 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0); in si_enable_uvd_mgcg() 5447 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0); in si_enable_uvd_mgcg() 5458 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0xffffffff); in si_enable_uvd_mgcg() 5459 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0xffffffff); in si_enable_uvd_mgcg()
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| A D | radeon.h | 2523 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) macro 2557 WREG32_SMC(reg, tmp_); \
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| A D | si_dpm.c | 2700 WREG32_SMC(offset, data); in si_program_cac_config_registers()
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| /linux/drivers/gpu/drm/amd/pm/legacy-dpm/ |
| A D | si_smc.c | 117 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in amdgpu_si_start_smc() 131 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in amdgpu_si_reset_smc() 150 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in amdgpu_si_smc_clock()
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| A D | kv_dpm.c | 524 WREG32_SMC(ixLCAC_SX0_OVR_SEL, 0); 525 WREG32_SMC(ixLCAC_SX0_OVR_VAL, 0); 528 WREG32_SMC(ixLCAC_MC0_OVR_SEL, 0); 529 WREG32_SMC(ixLCAC_MC0_OVR_VAL, 0); 532 WREG32_SMC(ixLCAC_MC1_OVR_SEL, 0); 533 WREG32_SMC(ixLCAC_MC1_OVR_VAL, 0); 536 WREG32_SMC(ixLCAC_MC2_OVR_SEL, 0); 537 WREG32_SMC(ixLCAC_MC2_OVR_VAL, 0); 540 WREG32_SMC(ixLCAC_MC3_OVR_SEL, 0); 541 WREG32_SMC(ixLCAC_MC3_OVR_VAL, 0); [all …]
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| A D | si_dpm.c | 2860 WREG32_SMC(offset, data); in si_program_cac_config_registers() 7557 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); in si_dpm_set_interrupt_state() 7562 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); in si_dpm_set_interrupt_state() 7574 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); in si_dpm_set_interrupt_state() 7579 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); in si_dpm_set_interrupt_state()
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | cik.c | 997 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK); in cik_read_disabled_bios() 1008 WREG32_SMC(ixROM_CNTL, rom_cntl); in cik_read_disabled_bios() 1468 WREG32_SMC(cntl_reg, tmp); in cik_set_uvd_clock() 1517 WREG32_SMC(ixCG_ECLK_CNTL, tmp); in cik_set_vce_clocks() 1797 WREG32_SMC(ixTHM_CLK_CNTL, data); in cik_program_aspm() 1805 WREG32_SMC(ixMISC_CLK_CTRL, data); in cik_program_aspm() 1810 WREG32_SMC(ixCG_CLKPIN_CNTL, data); in cik_program_aspm() 1815 WREG32_SMC(ixCG_CLKPIN_CNTL_2, data); in cik_program_aspm() 1821 WREG32_SMC(ixMPLL_BYPASSCLK_SEL, data); in cik_program_aspm()
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| A D | vi.c | 620 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK); in vi_read_disabled_bios() 631 WREG32_SMC(ixROM_CNTL, rom_cntl); in vi_read_disabled_bios() 1002 WREG32_SMC(cntl_reg, tmp); in vi_set_uvd_clock() 1092 WREG32_SMC(reg_ctrl, tmp); in vi_set_vce_clocks() 1192 WREG32_SMC(ixTHM_CLK_CNTL, data); in vi_program_aspm() 1201 WREG32_SMC(ixMISC_CLK_CTRL, data); in vi_program_aspm() 1206 WREG32_SMC(ixCG_CLKPIN_CNTL, data); in vi_program_aspm() 1211 WREG32_SMC(ixCG_CLKPIN_CNTL, data); in vi_program_aspm() 1217 WREG32_SMC(ixMPLL_BYPASSCLK_SEL, data); in vi_program_aspm() 1847 WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data); in vi_update_rom_medium_grain_clock_gating()
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| A D | amdgpu_cgs.c | 94 return WREG32_SMC(index, value); in amdgpu_cgs_write_ind_register()
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| A D | amdgpu.h | 1299 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) macro 1332 WREG32_SMC(_Reg, tmp); \
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| A D | vce_v4_0.c | 911 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
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| A D | uvd_v7_0.c | 1722 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
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| A D | amdgpu_debugfs.c | 848 WREG32_SMC(*pos, value); in amdgpu_debugfs_regs_smc_write()
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| A D | gfx_v8_0.c | 802 WREG32_SMC(ixCG_ACLK_CNTL, data); in gfx_v8_0_init_golden_registers()
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