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Searched refs:WREG32_SOC15_DPG_MODE (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
A Dvcn_v4_0_5.c462 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_5_mc_resume_dpg_mode()
500 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_5_mc_resume_dpg_mode()
504 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_5_mc_resume_dpg_mode()
508 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_5_mc_resume_dpg_mode()
512 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_5_mc_resume_dpg_mode()
514 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_5_mc_resume_dpg_mode()
518 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_5_mc_resume_dpg_mode()
521 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_5_mc_resume_dpg_mode()
524 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_5_mc_resume_dpg_mode()
526 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_5_mc_resume_dpg_mode()
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A Dvcn_v4_0_3.c520 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_3_mc_resume_dpg_mode()
524 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_3_mc_resume_dpg_mode()
528 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_3_mc_resume_dpg_mode()
532 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_3_mc_resume_dpg_mode()
534 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_3_mc_resume_dpg_mode()
538 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_3_mc_resume_dpg_mode()
541 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_3_mc_resume_dpg_mode()
785 WREG32_SOC15_DPG_MODE(inst_idx, 0xDEADBEEF, in vcn_v4_0_3_start_dpg_mode()
1914 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v4_0_3_enable_ras()
1919 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v4_0_3_enable_ras()
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A Dvcn_v2_5.c580 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode()
584 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode()
587 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode()
590 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode()
592 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode()
596 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode()
599 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode()
602 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode()
852 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v2_6_enable_ras()
857 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v2_6_enable_ras()
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A Dvcn_v2_0.c494 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( in vcn_v2_0_mc_resume_dpg_mode()
498 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( in vcn_v2_0_mc_resume_dpg_mode()
501 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( in vcn_v2_0_mc_resume_dpg_mode()
504 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( in vcn_v2_0_mc_resume_dpg_mode()
506 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( in vcn_v2_0_mc_resume_dpg_mode()
510 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( in vcn_v2_0_mc_resume_dpg_mode()
513 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( in vcn_v2_0_mc_resume_dpg_mode()
516 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( in vcn_v2_0_mc_resume_dpg_mode()
518 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( in vcn_v2_0_mc_resume_dpg_mode()
523 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( in vcn_v2_0_mc_resume_dpg_mode()
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A Dvcn_v4_0.c548 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_mc_resume_dpg_mode()
552 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_mc_resume_dpg_mode()
555 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_mc_resume_dpg_mode()
558 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_mc_resume_dpg_mode()
560 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_mc_resume_dpg_mode()
564 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_mc_resume_dpg_mode()
567 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_mc_resume_dpg_mode()
570 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_mc_resume_dpg_mode()
572 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_mc_resume_dpg_mode()
940 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v4_0_enable_ras()
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A Dvcn_v3_0.c606 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode()
610 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode()
613 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode()
616 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode()
618 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode()
622 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode()
625 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode()
628 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode()
630 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode()
635 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode()
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A Damdgpu_vcn.h144 #define WREG32_SOC15_DPG_MODE(inst_idx, offset, value, mask_en, indirect) \ macro

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