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Searched refs:amdgpu_ip_version (Results 1 – 25 of 111) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
A Dhdp_v4_0.c52 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 0) || in hdp_v4_0_invalidate_hdp()
53 amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 2) || in hdp_v4_0_invalidate_hdp()
54 amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 5)) in hdp_v4_0_invalidate_hdp()
84 if (amdgpu_ip_version(adev, HDP_HWIP, 0) >= IP_VERSION(4, 4, 0)) in hdp_v4_0_reset_ras_error_count()
96 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 0, 0) || in hdp_v4_0_update_clock_gating()
97 amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 0, 1) || in hdp_v4_0_update_clock_gating()
98 amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 1, 1) || in hdp_v4_0_update_clock_gating()
99 amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 1, 0)) { in hdp_v4_0_update_clock_gating()
133 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 2) || in hdp_v4_0_get_clockgating_state()
147 switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) { in hdp_v4_0_init_registers()
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A Dgmc_v9_0.c689 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in gmc_v9_0_process_interrupt()
1140 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v9_0_get_coherence_flags()
1154 if ((amdgpu_ip_version(adev, GC_HWIP, 0) == in gmc_v9_0_get_coherence_flags()
1156 amdgpu_ip_version(adev, GC_HWIP, 0) == in gmc_v9_0_get_coherence_flags()
1350 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { in gmc_v9_0_get_vbios_fb_size()
1421 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { in gmc_v9_0_set_umc_funcs()
1476 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in gmc_v9_0_set_mmhub_funcs()
1494 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in gmc_v9_0_set_mmhub_ras_funcs()
1532 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { in gmc_v9_0_set_mca_ras_funcs()
1727 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v9_0_mc_init()
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A Damdgpu_discovery.c1833 amdgpu_ip_version(adev, GC_HWIP, 0)); in amdgpu_discovery_set_common_ip_blocks()
1886 amdgpu_ip_version(adev, GC_HWIP, 0)); in amdgpu_discovery_set_gmc_ip_blocks()
1992 amdgpu_ip_version(adev, MP0_HWIP, 0)); in amdgpu_discovery_set_psp_ip_blocks()
2049 amdgpu_ip_version(adev, MP1_HWIP, 0)); in amdgpu_discovery_set_smu_ip_blocks()
2108 amdgpu_ip_version(adev, DCE_HWIP, 0)); in amdgpu_discovery_set_display_ip_blocks()
2124 amdgpu_ip_version(adev, DCI_HWIP, 0)); in amdgpu_discovery_set_display_ip_blocks()
2180 amdgpu_ip_version(adev, GC_HWIP, 0)); in amdgpu_discovery_set_gc_ip_blocks()
2235 amdgpu_ip_version(adev, SDMA0_HWIP, 0)); in amdgpu_discovery_set_sdma_ip_blocks()
2254 amdgpu_ip_version(adev, UVD_HWIP, 0)); in amdgpu_discovery_set_mm_ip_blocks()
2267 amdgpu_ip_version(adev, VCE_HWIP, 0)); in amdgpu_discovery_set_mm_ip_blocks()
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A Dathub_v4_1_0.c34 switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) { in athub_v4_1_0_get_cg_cntl()
47 switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) { in athub_v4_1_0_set_cg_cntl()
96 switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) { in athub_v4_1_0_set_clockgating()
A Dathub_v3_0.c41 switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) { in athub_v3_0_get_cg_cntl()
57 switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) { in athub_v3_0_set_cg_cntl()
110 switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) { in athub_v3_0_set_clockgating()
A Dvega20_ih.c295 if ((amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 2, 1)) && in vega20_ih_irq_init()
308 if ((amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 0)) || in vega20_ih_irq_init()
309 (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 2)) || in vega20_ih_irq_init()
310 (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 5))) { in vega20_ih_irq_init()
340 if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 0) || in vega20_ih_irq_init()
341 amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 2) || in vega20_ih_irq_init()
342 amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 5)) in vega20_ih_irq_init()
550 (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 2))) in vega20_ih_sw_init()
567 if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) != IP_VERSION(4, 4, 2) && in vega20_ih_sw_init()
568 amdgpu_ip_version(adev, OSSSYS_HWIP, 0) != IP_VERSION(4, 4, 5)) { in vega20_ih_sw_init()
A Dgmc_v10_0.c147 (amdgpu_ip_version(adev, GC_HWIP, 0) < in gmc_v10_0_process_interrupt()
312 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 3, 0))) in gmc_v10_0_flush_gpu_tlb()
584 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { in gmc_v10_0_set_umc_funcs()
601 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in gmc_v10_0_set_mmhub_funcs()
615 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v10_0_set_gfxhub_funcs()
731 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v10_0_mc_init()
798 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v10_0_sw_init()
816 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v10_0_sw_init()
1108 amdgpu_ip_version(adev, DF_HWIP, 0) > IP_VERSION(3, 0, 2)) { in gmc_v10_0_set_clockgating_state()
1117 if (amdgpu_ip_version(adev, ATHUB_HWIP, 0) >= IP_VERSION(2, 1, 0)) in gmc_v10_0_set_clockgating_state()
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A Dsoc15.c177 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) { in soc15_query_video_codecs()
178 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) { in soc15_query_video_codecs()
190 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { in soc15_query_video_codecs()
327 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(12, 0, 0) || in soc15_get_xclk()
328 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(12, 0, 1) || in soc15_get_xclk()
330 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 14)) in soc15_get_xclk()
333 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(10, 0, 1)) in soc15_get_xclk()
527 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in soc15_asic_reset_method()
627 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in soc15_supports_baco()
961 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in soc15_common_early_init()
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A Dvpe_v6_1.c135 if (amdgpu_ip_version(adev, VPE_HWIP, 0) == IP_VERSION(6, 1, 1)) in vpe_v6_1_load_microcode()
142 if (amdgpu_ip_version(adev, VPE_HWIP, 0) == IP_VERSION(6, 1, 1)) in vpe_v6_1_load_microcode()
283 if (amdgpu_ip_version(adev, VPE_HWIP, 0) == IP_VERSION(6, 1, 1)) in vpe_v_6_1_ring_stop()
290 if (amdgpu_ip_version(adev, VPE_HWIP, 0) == IP_VERSION(6, 1, 1)) { in vpe_v_6_1_ring_stop()
317 if (amdgpu_ip_version(adev, VPE_HWIP, 0) == IP_VERSION(6, 1, 1)) in vpe_v6_1_set_trap_irq_state()
325 if (amdgpu_ip_version(adev, VPE_HWIP, 0) == IP_VERSION(6, 1, 1)) in vpe_v6_1_set_trap_irq_state()
361 if (amdgpu_ip_version(adev, VPE_HWIP, 0) == IP_VERSION(6, 1, 1)) in vpe_v6_1_set_regs()
A Dhdp_v6_0.c54 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(6, 1, 0)) in hdp_v6_0_update_clock_gating()
64 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(6, 1, 0)) in hdp_v6_0_update_clock_gating()
129 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(6, 1, 0)) in hdp_v6_0_update_clock_gating()
A Dpsp_v13_0.c94 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { in psp_v13_0_init_microcode()
179 ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || in psp_v13_0_wait_for_bootloader()
180 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14))) ? in psp_v13_0_wait_for_bootloader()
205 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || in psp_v13_0_wait_for_bootloader_steady_state()
206 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) { in psp_v13_0_wait_for_bootloader_steady_state()
770 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 10)) { in psp_v13_0_fatal_error_recovery_quirk()
800 if ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || in psp_v13_0_get_ras_capability()
801 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) && in psp_v13_0_get_ras_capability()
817 if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) in psp_v13_0_is_aux_sos_load_required()
A Dnbio_v7_2.c62 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in nbio_v7_2_get_rev_id()
81 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in nbio_v7_2_mc_access_enable()
265 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in nbio_v7_2_update_medium_grain_light_sleep()
372 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in nbio_v7_2_init_registers()
397 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in nbio_v7_2_init_registers()
A Dsoc24.c80 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { in soc24_query_video_codecs()
205 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in soc24_asic_reset_method()
263 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in soc24_need_full_reset()
389 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in soc24_common_early_init()
549 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in soc24_common_set_clockgating_state()
569 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) { in soc24_common_set_powergating_state()
A Dumsch_mm_v4_0.c64 if (amdgpu_ip_version(adev, VCN_HWIP, 0) >= IP_VERSION(4, 0, 5)) { in umsch_mm_v4_0_load_microcode()
258 if (amdgpu_ip_version(adev, VCN_HWIP, 0) >= IP_VERSION(4, 0, 5)) { in umsch_mm_v4_0_ring_stop()
298 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, MMHUB_HWIP, 0)); in umsch_mm_v4_0_set_hw_resources()
303 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, OSSSYS_HWIP, 0)); in umsch_mm_v4_0_set_hw_resources()
306 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VCN_HWIP, 0)); in umsch_mm_v4_0_set_hw_resources()
308 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VPE_HWIP, 0)); in umsch_mm_v4_0_set_hw_resources()
A Dmmhub_v2_0.c154 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in mmhub_v2_0_print_l2_protection_fault_status()
571 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in mmhub_v2_0_update_medium_grain_clock_gating()
604 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in mmhub_v2_0_update_medium_grain_clock_gating()
628 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in mmhub_v2_0_update_medium_grain_light_sleep()
654 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in mmhub_v2_0_set_clockgating()
679 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in mmhub_v2_0_get_clockgating()
A Damdgpu_reset.c33 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in amdgpu_reset_init()
56 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in amdgpu_reset_fini()
A Dsdma_v4_0.c519 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { in sdma_v4_0_init_golden_registers()
589 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { in sdma_v4_0_setup_ulv()
628 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == in sdma_v4_0_init_microcode()
630 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == in sdma_v4_0_init_microcode()
1026 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == in sdma_v4_0_ctx_switch_enable()
1863 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == in sdma_v4_0_sw_init()
1885 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) >= in sdma_v4_0_sw_init()
1887 amdgpu_ip_version(adev, SDMA0_HWIP, 0) < in sdma_v4_0_sw_init()
1900 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == in sdma_v4_0_sw_init()
2090 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == in sdma_v4_0_process_trap_irq()
[all …]
A Dsoc21.c156 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { in soc21_query_video_codecs()
383 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in soc21_asic_reset_method()
459 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in soc21_need_full_reset()
584 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in soc21_common_early_init()
952 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in soc21_common_set_clockgating_state()
978 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) { in soc21_common_set_powergating_state()
A Daldebaran.c38 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 2) && in aldebaran_is_mode2_default()
157 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 2) && in aldebaran_mode2_perform_reset()
337 if (amdgpu_ip_version(reset_context->reset_req_dev, MP1_HWIP, 0) == in aldebaran_mode2_restore_hwcontext()
A Damdgpu_psp.c104 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { in psp_check_pmfw_centralized_cstate_management()
132 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { in psp_init_sriov_microcode()
170 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { in psp_early_init()
865 switch (amdgpu_ip_version(psp->adev, MP0_HWIP, 0)) { in psp_skip_tmr()
1358 return (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == in psp_xgmi_peer_link_info_supported()
1361 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= in psp_xgmi_peer_link_info_supported()
1477 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == in psp_xgmi_get_topology_info()
1479 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == in psp_xgmi_get_topology_info()
2836 (amdgpu_ip_version(adev, MP0_HWIP, 0) == in psp_load_non_psp_fw()
2838 amdgpu_ip_version(adev, MP0_HWIP, 0) == in psp_load_non_psp_fw()
[all …]
A Dgmc_v11_0.c547 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { in gmc_v11_0_set_umc_funcs()
570 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in gmc_v11_0_set_mmhub_funcs()
589 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v11_0_set_gfxhub_funcs()
652 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(11, 5, 0)) && in gmc_v11_0_vram_gtt_location()
750 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v11_0_sw_init()
A Dgmc_v12_0.c549 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 0, 0) && in gmc_v12_0_get_dcc_alignment()
550 amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 0, 1)) in gmc_v12_0_get_dcc_alignment()
586 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in gmc_v12_0_set_mmhub_funcs()
597 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v12_0_set_gfxhub_funcs()
752 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v12_0_sw_init()
/linux/drivers/gpu/drm/amd/amdkfd/
A Dkfd_int_process_v9.c170 if (amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) { in event_interrupt_poison_consumption_v9()
177 } else if (amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) { in event_interrupt_poison_consumption_v9()
199 if (amdgpu_ip_version(dev->adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2)) { in event_interrupt_poison_consumption_v9()
206 } else if (amdgpu_ip_version(dev->adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) { in event_interrupt_poison_consumption_v9()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
A Dyellow_carp_ppt.c1011 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 8)) in yellow_carp_get_umd_pstate_clk_default()
1013 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 1) || in yellow_carp_get_umd_pstate_clk_default()
1014 (amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 3)) in yellow_carp_get_umd_pstate_clk_default()
1018 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 8)) in yellow_carp_get_umd_pstate_clk_default()
1020 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 1) || in yellow_carp_get_umd_pstate_clk_default()
1021 (amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 3)) in yellow_carp_get_umd_pstate_clk_default()
1025 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 8)) in yellow_carp_get_umd_pstate_clk_default()
1027 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 1) || in yellow_carp_get_umd_pstate_clk_default()
1028 (amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 3)) in yellow_carp_get_umd_pstate_clk_default()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
A Dsmu_v11_0.c103 ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 9)) || in smu_v11_0_init_microcode()
104 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 7)))) in smu_v11_0_init_microcode()
212 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in smu_v11_0_check_fw_version()
245 amdgpu_ip_version(adev, MP1_HWIP, 0)); in smu_v11_0_check_fw_version()
473 size_t size = amdgpu_ip_version(adev, MP1_HWIP, 0) == in smu_v11_0_init_power()
731 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 11) || in smu_v11_0_init_display_count()
732 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 0) || in smu_v11_0_init_display_count()
734 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 13)) in smu_v11_0_init_display_count()
1103 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in smu_v11_0_gfx_off_control()
1601 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in smu_v11_0_baco_set_state()
[all …]

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