| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | hdp_v4_0.c | 46 …amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> … in hdp_v4_0_flush_hdp()
60 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( in hdp_v4_0_invalidate_hdp()
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| A D | hdp_v5_0.c | 37 …amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> … in hdp_v5_0_flush_hdp()
46 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( in hdp_v5_0_invalidate_hdp()
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| A D | gmc_v11_0.c | 361 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + in gmc_v11_0_emit_flush_gpu_tlb()
365 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + in gmc_v11_0_emit_flush_gpu_tlb()
381 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + in gmc_v11_0_emit_flush_gpu_tlb()
402 amdgpu_ring_emit_wreg(ring, reg, pasid); in gmc_v11_0_emit_pasid_mapping()
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| A D | gmc_v12_0.c | 381 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + in gmc_v12_0_emit_flush_gpu_tlb()
385 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + in gmc_v12_0_emit_flush_gpu_tlb()
401 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + in gmc_v12_0_emit_flush_gpu_tlb()
422 amdgpu_ring_emit_wreg(ring, reg, pasid); in gmc_v12_0_emit_pasid_mapping()
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| A D | hdp_v7_0.c | 37 …amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> … in hdp_v7_0_flush_hdp()
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| A D | gmc_v10_0.c | 396 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + in gmc_v10_0_emit_flush_gpu_tlb()
400 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + in gmc_v10_0_emit_flush_gpu_tlb()
416 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + in gmc_v10_0_emit_flush_gpu_tlb()
437 amdgpu_ring_emit_wreg(ring, reg, pasid); in gmc_v10_0_emit_pasid_mapping()
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| A D | hdp_v6_0.c | 40 …amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> … in hdp_v6_0_flush_hdp()
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| A D | hdp_v5_2.c | 38 amdgpu_ring_emit_wreg(ring, in hdp_v5_2_flush_hdp()
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| A D | gmc_v6_0.c | 358 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); in gmc_v6_0_emit_flush_gpu_tlb()
361 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); in gmc_v6_0_emit_flush_gpu_tlb()
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| A D | gmc_v7_0.c | 475 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); in gmc_v7_0_emit_flush_gpu_tlb()
478 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); in gmc_v7_0_emit_flush_gpu_tlb()
486 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); in gmc_v7_0_emit_pasid_mapping()
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| A D | gmc_v9_0.c | 998 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + in gmc_v9_0_emit_flush_gpu_tlb()
1002 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + in gmc_v9_0_emit_flush_gpu_tlb()
1018 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + in gmc_v9_0_emit_flush_gpu_tlb()
1039 amdgpu_ring_emit_wreg(ring, reg, pasid); in gmc_v9_0_emit_pasid_mapping()
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| A D | gmc_v8_0.c | 666 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); in gmc_v8_0_emit_flush_gpu_tlb()
669 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); in gmc_v8_0_emit_flush_gpu_tlb()
677 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); in gmc_v8_0_emit_pasid_mapping()
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| A D | sdma_v6_0.c | 1205 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + in sdma_v6_0_ring_emit_vm_flush()
1208 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + in sdma_v6_0_ring_emit_vm_flush()
1252 amdgpu_ring_emit_wreg(ring, reg0, ref); in sdma_v6_0_ring_emit_reg_write_reg_wait()
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| A D | amdgpu_ring.c | 424 amdgpu_ring_emit_wreg(ring, reg0, ref); in amdgpu_ring_emit_reg_write_reg_wait_helper()
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| A D | amdgpu_ring.h | 329 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v)) macro
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| A D | cik.c | 1864 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); in cik_flush_hdp()
1875 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1); in cik_invalidate_hdp()
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| A D | vi.c | 1317 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); in vi_flush_hdp()
1328 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1); in vi_invalidate_hdp()
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| A D | si.c | 1489 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); in si_flush_hdp()
1500 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1); in si_invalidate_hdp()
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| A D | sdma_v7_0.c | 1256 amdgpu_ring_emit_wreg(ring, reg0, ref); in sdma_v7_0_ring_emit_reg_write_reg_wait()
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| A D | amdgpu_gfx.c | 1109 amdgpu_ring_emit_wreg(ring, reg, v); in amdgpu_kiq_wreg()
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| A D | sdma_v5_2.c | 1213 amdgpu_ring_emit_wreg(ring, reg0, ref); in sdma_v5_2_ring_emit_reg_write_reg_wait()
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| A D | sdma_v5_0.c | 1363 amdgpu_ring_emit_wreg(ring, reg0, ref); in sdma_v5_0_ring_emit_reg_write_reg_wait()
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| A D | gfx_v9_0.c | 5743 amdgpu_ring_emit_wreg(ring, in gfx_v9_0_ring_preempt_ib()
7137 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); in gfx_v9_0_emit_wave_limit_cs()
7152 amdgpu_ring_emit_wreg(ring, in gfx_v9_0_emit_wave_limit()
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| A D | gfx_v9_4_3.c | 3446 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); in gfx_v9_4_3_emit_wave_limit_cs()
3460 amdgpu_ring_emit_wreg(ring, in gfx_v9_4_3_emit_wave_limit()
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| A D | gfx_v8_0.c | 6858 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); in gfx_v8_0_emit_wave_limit_cs()
6874 amdgpu_ring_emit_wreg(ring, mmSPI_WCL_PIPE_PERCENT_GFX, val); in gfx_v8_0_emit_wave_limit()
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