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/linux/tools/perf/Documentation/
A Dperf-c2c.txt20 you to track down the cacheline contentions.
88 Specify sorting fields for single cacheline display.
134 Group the detection of shared cacheline events into double cacheline
136 feature, which causes cacheline sharing to behave like the cacheline
178 - store access details for each cacheline
184 2) offsets details for each cacheline
190 - zero based index to identify the cacheline
193 - cacheline address (hex number)
199 - cacheline percentage of all peer accesses
245 level for given offset within cacheline
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A Dperf-mem.txt105 - dcacheline: the cacheline the data address is on at the time of the sample
A Dperf-amd-ibs.txt158 cacheline analyser tool. Both of them internally uses IBS Op PMU on AMD.
/linux/drivers/gpu/drm/i915/gt/
A Dintel_ring.h111 #define cacheline(a) round_down(a, CACHELINE_BYTES) in assert_ring_tail_valid() macro
112 GEM_BUG_ON(cacheline(tail) == cacheline(head) && tail < head); in assert_ring_tail_valid()
113 #undef cacheline in assert_ring_tail_valid()
A Dselftest_timeline.c97 unsigned long cacheline; in __mock_hwsp_timeline() local
110 cacheline = hwsp_cacheline(tl); in __mock_hwsp_timeline()
111 err = radix_tree_insert(&state->cachelines, cacheline, tl); in __mock_hwsp_timeline()
115 cacheline); in __mock_hwsp_timeline()
/linux/include/asm-generic/
A Dvmlinux.lds.h1035 #define PERCPU_INPUT(cacheline) \ argument
1040 . = ALIGN(cacheline); \
1042 . = ALIGN(cacheline); \
1072 #define PERCPU_VADDR(cacheline, vaddr, phdr) \ argument
1075 PERCPU_INPUT(cacheline) \
1091 #define PERCPU_SECTION(cacheline) \ argument
1095 PERCPU_INPUT(cacheline) \
1117 #define RW_DATA(cacheline, pagealigned, inittask) \ argument
1123 CACHELINE_ALIGNED_DATA(cacheline) \
1124 READ_MOSTLY_DATA(cacheline) \
/linux/drivers/soc/qcom/
A Dsmem.c155 __le32 cacheline; member
209 size_t cacheline; member
301 size_t cacheline) in phdr_to_first_cached_entry() argument
306 return p + le32_to_cpu(phdr->size) - ALIGN(sizeof(*e), cacheline); in phdr_to_first_cached_entry()
335 cached_entry_next(struct smem_private_entry *e, size_t cacheline) in cached_entry_next() argument
339 return p - le32_to_cpu(e->size) - ALIGN(sizeof(*e), cacheline); in cached_entry_next()
629 e = phdr_to_first_cached_entry(phdr, part->cacheline); in qcom_smem_get_private()
657 e = cached_entry_next(e, part->cacheline); in qcom_smem_get_private()
1000 smem->global_partition.cacheline = le32_to_cpu(entry->cacheline); in qcom_smem_set_global_partition()
1053 smem->partitions[remote_host].cacheline = le32_to_cpu(entry->cacheline); in qcom_smem_enumerate_partitions()
/linux/drivers/md/bcache/
A Dbset.c530 unsigned int cacheline, in cacheline_to_bkey() argument
533 return ((void *) t->data) + cacheline * BSET_CACHELINE + offset * 8; in cacheline_to_bkey()
542 unsigned int cacheline, in bkey_to_cacheline_offset() argument
545 return (u64 *) k - (u64 *) cacheline_to_bkey(t, cacheline, 0); in bkey_to_cacheline_offset()
562 static struct bkey *table_to_bkey(struct bset_tree *t, unsigned int cacheline) in table_to_bkey() argument
564 return cacheline_to_bkey(t, cacheline, t->prev[cacheline]); in table_to_bkey()
698 unsigned int j, cacheline = 1; in bch_bset_build_written_tree() local
719 while (bkey_to_cacheline(t, k) < cacheline) { in bch_bset_build_written_tree()
725 t->tree[j].m = bkey_to_cacheline_offset(t, cacheline++, k); in bch_bset_build_written_tree()
/linux/fs/bcachefs/
A Dbset.c418 unsigned cacheline) in bset_cacheline() argument
422 cacheline * BSET_CACHELINE; in bset_cacheline()
427 unsigned cacheline, in cacheline_to_bkey() argument
430 return bset_cacheline(b, t, cacheline) + offset * 8; in cacheline_to_bkey()
442 unsigned cacheline, in __bkey_to_cacheline_offset() argument
445 return (u64 *) k - (u64 *) bset_cacheline(b, t, cacheline); in __bkey_to_cacheline_offset()
450 unsigned cacheline, in bkey_to_cacheline_offset() argument
453 size_t m = __bkey_to_cacheline_offset(b, t, cacheline, k); in bkey_to_cacheline_offset()
700 unsigned cacheline = 1; in __build_ro_aux_tree() local
715 while (bkey_to_cacheline(b, t, k) < cacheline) in __build_ro_aux_tree()
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/linux/Documentation/translations/zh_CN/locking/
A Dmutex-design.rst60cacheline bouncing)这种昂贵的开销。一个类MCS锁是为实现睡眠锁的
/linux/kernel/
A DKconfig.hz14 contention and cacheline bounces as a result of timer interrupts.
/linux/Documentation/arch/sparc/
A Dadi.rst35 size is same as cacheline size which is 64 bytes. A task that sets ADI
103 the corresponding cacheline, a memory corruption trap occurs. By
123 the corresponding cacheline, a memory corruption trap occurs. If
/linux/arch/sparc/kernel/
A Dprom_irqtrans.c356 static unsigned char cacheline[64] in tomatillo_wsync_handler() local
367 "i" (FPRS_FEF), "r" (&cacheline[0]), in tomatillo_wsync_handler()
A Dcherrs.S203 sub %g1, %g2, %g1 ! Move down 1 cacheline
215 subcc %g1, %g2, %g1 ! Next cacheline
/linux/Documentation/translations/zh_CN/core-api/
A Dcachetlb.rst196 加载到不同的cacheline中就会出现别名现象。
/linux/arch/parisc/kernel/
A Dperf_asm.S132 ; Cacheline start (32-byte cacheline)
145 ; Cacheline start (32-byte cacheline)
/linux/Documentation/locking/
A Dmutex-design.rst55 cacheline bouncing that common test-and-set spinlock implementations
/linux/Documentation/kernel-hacking/
A Dfalse-sharing.rst66 cache hot and save cacheline/TLB, like a lock and the data protected
/linux/Documentation/
A Datomic_t.txt358 loop body. As a result there is no guarantee what so ever the cacheline
/linux/Documentation/arch/x86/
A Dtdx.rst156 write to a TDX private memory cacheline will silently "poison" the
161 cacheline lands at the memory controller. The CPU does these via
/linux/Documentation/driver-api/
A Dedac.rst46 lockstep is enabled, the cacheline is doubled, but it generally brings
/linux/Documentation/mm/
A Dmultigen_lru.rst191 promotes hot pages. If the scan was done cacheline efficiently, it
/linux/security/
A DKconfig.hardening362 best effort at restricting randomization to cacheline-sized
/linux/tools/perf/util/
A DBuild10 perf-util-y += cacheline.o
/linux/Documentation/networking/device_drivers/ethernet/amazon/
A Dena.rst28 and CPU cacheline optimized data placement.

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