| /linux/drivers/gpu/drm/i915/display/ |
| A D | intel_cdclk.c | 629 int cdclk = cdclk_config->cdclk; in vlv_set_cdclk() local
718 int cdclk = cdclk_config->cdclk; in chv_set_cdclk() local
837 int cdclk = cdclk_config->cdclk; in bdw_set_cdclk() local
1118 int cdclk = cdclk_config->cdclk; in skl_set_cdclk() local
1499 table[i].cdclk == cdclk) in bxt_calc_cdclk_pll_vco()
1844 table[i].cdclk == cdclk) in cdclk_squash_waveform()
2011 int cdclk = cdclk_config->cdclk; in bxt_cdclk_ctl() local
2171 if (cdclk != dev_priv->display.cdclk.hw.cdclk) in bxt_sanitize_cdclk()
2335 return a->cdclk != b->cdclk && in intel_cdclk_can_squash()
2353 return a->cdclk != b->cdclk || in intel_cdclk_clock_changed()
[all …]
|
| A D | intel_cdclk.h | 19 unsigned int cdclk, vco, ref, bypass; member
91 …k_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
93 …k_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
|
| A D | intel_audio.c | 441 unsigned int fec_coeff, cdclk, vdsc_bppx16; in calc_hblank_early_prog() local
449 cdclk = i915->display.cdclk.hw.cdclk; in calc_hblank_early_prog()
457 h_active, link_clk, lanes, FXP_Q4_ARGS(vdsc_bppx16), cdclk); in calc_hblank_early_prog()
459 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 || !cdclk)) in calc_hblank_early_prog()
468 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), in calc_hblank_early_prog()
469 mul_u32_u32(link_clk, cdclk)); in calc_hblank_early_prog()
904 static void get_aud_ts_cdclk_m_n(int refclk, int cdclk, struct aud_ts_cdclk_m_n *aud_ts) in get_aud_ts_cdclk_m_n() argument
907 aud_ts->n = cdclk * aud_ts->m / 24000; in get_aud_ts_cdclk_m_n()
915 get_aud_ts_cdclk_m_n(i915->display.cdclk.hw.ref, i915->display.cdclk.hw.cdclk, &aud_ts); in intel_audio_cdclk_change_post()
1065 return i915->display.cdclk.hw.cdclk; in i915_audio_component_get_cdclk_freq()
|
| A D | intel_display_driver.c | 90 cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state); in intel_display_driver_init_hw()
93 intel_cdclk_dump_config(i915, &i915->display.cdclk.hw, "Current CDCLK"); in intel_display_driver_init_hw()
94 cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw; in intel_display_driver_init_hw()
453 if (i915->display.cdclk.max_cdclk_freq == 0) in intel_display_driver_probe_nogem()
|
| A D | intel_display_core.h | 295 const struct intel_cdclk_funcs *cdclk; member
354 } cdclk; member
|
| A D | hsw_ips.c | 210 crtc_state->pixel_rate > i915->display.cdclk.max_cdclk_freq * 95 / 100) in hsw_crtc_state_ips_capable()
249 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100) in hsw_ips_compute_config()
|
| A D | intel_pmdemand.c | 286 (new_cdclk_state->actual.cdclk != in intel_pmdemand_needs_update()
287 old_cdclk_state->actual.cdclk || in intel_pmdemand_needs_update()
342 DIV_ROUND_UP(new_cdclk_state->actual.cdclk, 1000); in intel_pmdemand_atomic_check()
|
| A D | intel_dsi.c | 67 int max_dotclk = to_i915(connector->dev)->display.cdclk.max_dotclk_freq; in intel_dsi_mode_valid()
|
| A D | intel_dp_aux.c | 106 freq = display->cdclk.hw.cdclk; in ilk_get_aux_clock_divider()
|
| A D | intel_modeset_setup.c | 158 to_intel_cdclk_state(i915->display.cdclk.obj.state); in intel_crtc_disable_noatomic_complete()
699 to_intel_cdclk_state(i915->display.cdclk.obj.state); in intel_modeset_readout_hw_state()
|
| A D | intel_backlight.c | 1096 clock = KHz(i915->display.cdclk.hw.cdclk); in i9xx_hz_to_pwm()
1114 clock = KHz(i915->display.cdclk.hw.cdclk); in i965_hz_to_pwm()
|
| A D | intel_dvo.c | 226 int max_dotclk = to_i915(connector->base.dev)->display.cdclk.max_dotclk_freq; in intel_dvo_mode_valid()
|
| A D | intel_lvds.c | 396 int max_pixclk = to_i915(connector->base.dev)->display.cdclk.max_dotclk_freq; in intel_lvds_mode_valid()
|
| A D | intel_crt.c | 351 int max_dotclk = dev_priv->display.cdclk.max_dotclk_freq; in intel_crt_mode_valid()
|
| A D | intel_dp.c | 883 i915->display.cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits / in get_max_compressed_bpp_with_joiner()
970 if (mode_clock >= ((i915->display.cdclk.max_cdclk_freq * 85) / 100)) in intel_dp_dsc_get_slice_count()
1282 return clock > i915->display.cdclk.max_dotclk_freq || hdisplay > 5120 || in intel_dp_need_joiner()
1316 int max_dotclk = dev_priv->display.cdclk.max_dotclk_freq; in intel_dp_mode_valid()
|
| A D | intel_display.c | 2482 int clock_limit = i915->display.cdclk.max_dotclk_freq; in intel_crtc_compute_pipe_mode()
2498 clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10; in intel_crtc_compute_pipe_mode()
2506 clock_limit = i915->display.cdclk.max_dotclk_freq; in intel_crtc_compute_pipe_mode()
4212 cdclk_state->logical.cdclk); in hsw_ips_linetime_wm()
7962 int max_dotclock = i915->display.cdclk.max_dotclk_freq; in max_dotclock()
|
| A D | intel_tv.c | 964 int max_dotclk = display->cdclk.max_dotclk_freq; in intel_tv_mode_valid()
|
| A D | intel_display_power_well.c | 988 intel_cdclk_clock_changed(&dev_priv->display.cdclk.hw, in gen9_disable_dc_states()
|
| A D | intel_fbc.c | 1419 if (crtc_state->pixel_rate >= cdclk_state->logical.cdclk * 95 / 100) { in intel_fbc_check_plane()
|
| A D | intel_dp_mst.c | 1442 int max_dotclk = to_i915(connector->dev)->display.cdclk.max_dotclk_freq; in intel_dp_mst_mode_valid_ctx()
|
| /linux/drivers/clk/samsung/ |
| A D | clk-s5pv210-audss.c | 70 struct clk *hclk, *pll_ref, *pll_in, *cdclk, *sclk_audio; in s5pv210_audss_clk_probe() local
105 cdclk = devm_clk_get(&pdev->dev, "iiscdclk0"); in s5pv210_audss_clk_probe()
119 if (!IS_ERR(cdclk)) in s5pv210_audss_clk_probe()
120 mout_i2s_p[1] = __clk_get_name(cdclk); in s5pv210_audss_clk_probe()
|
| A D | clk-exynos-audss.c | 128 struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in; in exynos_audss_clk_probe() local
188 cdclk = devm_clk_get(dev, "cdclk"); in exynos_audss_clk_probe()
190 if (!IS_ERR(cdclk)) in exynos_audss_clk_probe()
191 mout_i2s_p[1] = __clk_get_name(cdclk); in exynos_audss_clk_probe()
|
| /linux/Documentation/devicetree/bindings/clock/ |
| A D | samsung,exynos-audss-clock.yaml | 52 - const: cdclk
79 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
|
| /linux/arch/arm/boot/dts/samsung/ |
| A D | s3c64xx-pinctrl.dtsi | 334 i2s0_cdclk: i2s0-cdclk-pins {
346 i2s1_cdclk: i2s1-cdclk-pins {
360 i2s2_cdclk: i2s2-cdclk-pins {
|
| /linux/drivers/gpu/drm/i915/ |
| A D | i915_reg.h | 3532 #define DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \ argument
3533 ((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \
|