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Searched refs:clk_mgr (Results 1 – 25 of 106) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/
A Dclk_mgr.c154 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create() local
167 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create() local
177 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create() local
187 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create() local
280 struct clk_mgr_vgh *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create() local
292 struct clk_mgr_dcn31 *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create() local
304 struct clk_mgr_dcn315 *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create() local
316 struct clk_mgr_dcn316 *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create() local
339 struct clk_mgr_dcn314 *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create() local
352 struct clk_mgr_dcn35 *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create() local
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
A Ddcn30_clk_mgr.c49 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
52 (clk_mgr->regs->reg)
124 if (!clk_mgr->smu_present) in dcn3_init_clocks()
349 dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32); in dcn3_notify_wm_ranges()
350 dcn30_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF); in dcn3_notify_wm_ranges()
504 static void dcn3_init_clocks_fpga(struct clk_mgr *clk_mgr) in dcn3_init_clocks_fpga() argument
526 clk_mgr->base.ctx = ctx; in dcn3_clk_mgr_construct()
532 clk_mgr->dccg = dccg; in dcn3_clk_mgr_construct()
543 clk_mgr->base.dentist_vco_freq_khz = dcn30_get_vco_frequency_from_reg(clk_mgr); in dcn3_clk_mgr_construct()
562 clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL); in dcn3_clk_mgr_construct()
[all …]
A Ddcn30_clk_mgr_smu_msg.c183 dcn30_smu_send_msg_with_param(clk_mgr, in dcn30_smu_set_dram_addr_high()
191 dcn30_smu_send_msg_with_param(clk_mgr, in dcn30_smu_set_dram_addr_low()
199 dcn30_smu_send_msg_with_param(clk_mgr, in dcn30_smu_transfer_wm_table_smu_2_dram()
207 dcn30_smu_send_msg_with_param(clk_mgr, in dcn30_smu_transfer_wm_table_dram_2_smu()
221 dcn30_smu_send_msg_with_param(clk_mgr, in dcn30_smu_set_hard_min_by_freq()
239 dcn30_smu_send_msg_with_param(clk_mgr, in dcn30_smu_set_hard_max_by_freq()
270 dcn30_smu_send_msg_with_param(clk_mgr, in dcn30_smu_get_dpm_freq_by_index()
288 dcn30_smu_send_msg_with_param(clk_mgr, in dcn30_smu_get_dc_mode_max_dpm_freq()
300 dcn30_smu_send_msg_with_param(clk_mgr, in dcn30_smu_set_min_deep_sleep_dcef_clk()
308 dcn30_smu_send_msg_with_param(clk_mgr, in dcn30_smu_set_num_of_displays()
[all …]
A Ddcn30_clk_mgr_smu_msg.h33 bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input);
34 bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version);
35 bool dcn30_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr);
36 bool dcn30_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr);
37 void dcn30_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
38 void dcn30_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
39 void dcn30_smu_transfer_wm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
40 void dcn30_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
44 unsigned int dcn30_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk);
46 void dcn30_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t num_displays);
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
A Ddcn35_smu.c187 clk_mgr, in dcn35_smu_get_smu_version()
202 clk_mgr, in dcn35_smu_set_dispclk()
218 clk_mgr, in dcn35_smu_set_dprefclk()
235 clk_mgr, in dcn35_smu_set_hard_min_dcfclk()
252 clk_mgr, in dcn35_smu_set_min_deep_sleep_dcfclk()
269 clk_mgr, in dcn35_smu_set_dppclk()
288 clk_mgr, in dcn35_smu_set_display_idle_optimization()
307 clk_mgr, in dcn35_smu_enable_phy_refclk_pwrdwn()
319 clk_mgr, in dcn35_smu_enable_pme_wa()
409 clk_mgr, in dcn35_smu_set_zstate_support()
[all …]
A Ddcn35_clk_mgr.c199 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; in dcn35_update_clocks_update_dpp_dto()
505 static void init_clk_states(struct clk_mgr *clk_mgr) in init_clk_states() argument
520 void dcn35_init_clocks(struct clk_mgr *clk_mgr) in dcn35_init_clocks() argument
530 clk_mgr->dp_dto_source_clock_in_khz = clk_mgr->dprefclk_khz; in dcn35_init_clocks()
985 static void dcn35_init_clocks_fpga(struct clk_mgr *clk_mgr) in dcn35_init_clocks_fpga() argument
992 static void dcn35_update_clocks_fpga(struct clk_mgr *clk_mgr, in dcn35_update_clocks_fpga() argument
1045 if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz) in dcn35_update_clocks_fpga()
1046 clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz; in dcn35_update_clocks_fpga()
1047 if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz) in dcn35_update_clocks_fpga()
1048 clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz; in dcn35_update_clocks_fpga()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
A Ddcn32_clk_mgr.c86 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
89 (clk_mgr->regs->reg)
184 if (!clk_mgr->smu_present) in dcn32_init_clocks()
319 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; in dcn32_update_clocks_update_dpp_dto()
363 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz; in dcn32_update_clocks_update_dentist()
988 dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32); in dcn32_notify_wm_ranges()
1167 clk_mgr->dccg = dccg; in dcn32_clk_mgr_construct()
1199 clk_mgr->base.clks.ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) { in dcn32_clk_mgr_construct()
1200 clk_mgr->base.clks.ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk; in dcn32_clk_mgr_construct()
1204 clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk; in dcn32_clk_mgr_construct()
[all …]
A Ddcn32_clk_mgr_smu_msg.c74 dcn32_smu_wait_for_response(clk_mgr, 10, 200000); in dcn32_smu_send_msg_with_param()
85 TRACE_SMU_MSG(msg_id, param_in, clk_mgr->base.ctx); in dcn32_smu_send_msg_with_param()
123 TRACE_SMU_DELAY(*total_delay_us, clk_mgr->base.ctx); in dcn32_smu_wait_for_response_delay()
145 TRACE_SMU_MSG(msg_id, param_in, clk_mgr->base.ctx); in dcn32_smu_send_msg_with_param_delay()
164 dcn32_smu_send_msg_with_param(clk_mgr, in dcn32_smu_send_fclk_pstate_message()
180 dcn32_smu_send_msg_with_param(clk_mgr, in dcn32_smu_transfer_wm_table_dram_2_smu()
188 dcn32_smu_send_msg_with_param(clk_mgr, in dcn32_smu_set_pme_workaround()
196 if (clk_mgr->smu_ver >= 0x4e6a00) in dcn32_get_hard_min_status_supported()
199 if (clk_mgr->smu_ver >= 0x524e00) in dcn32_get_hard_min_status_supported()
202 if (clk_mgr->smu_ver >= 0x503900) in dcn32_get_hard_min_status_supported()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
A Ddcn316_smu.c155 clk_mgr, in dcn316_smu_get_smu_version()
170 clk_mgr, in dcn316_smu_set_dispclk()
188 clk_mgr, in dcn316_smu_set_hard_min_dcfclk()
206 clk_mgr, in dcn316_smu_set_min_deep_sleep_dcfclk()
221 clk_mgr, in dcn316_smu_set_dppclk()
238 clk_mgr, in dcn316_smu_set_display_idle_optimization()
256 clk_mgr, in dcn316_smu_enable_phy_refclk_pwrdwn()
303 clk_mgr, in dcn316_smu_enable_pme_wa()
315 clk_mgr, in dcn316_smu_set_dtbclk()
326 clk_mgr, in dcn316_smu_get_dpref_clk()
[all …]
A Ddcn316_clk_mgr.c404 if (!clk_mgr->smu_ver) in dcn316_notify_wm_ranges()
426 if (!clk_mgr->smu_ver) in dcn316_get_dpm_table_from_smu()
582 clk_mgr->base.base.ctx = ctx; in dcn316_clk_mgr_construct()
587 clk_mgr->base.dccg = dccg; in dcn316_clk_mgr_construct()
596 clk_mgr->base.base.ctx, in dcn316_clk_mgr_construct()
608 clk_mgr->base.base.ctx, in dcn316_clk_mgr_construct()
620 clk_mgr->base.smu_ver = dcn316_smu_get_smu_version(&clk_mgr->base); in dcn316_clk_mgr_construct()
644 clk_mgr->base.base.dprefclk_khz = dcn316_smu_get_dpref_clk(&clk_mgr->base); in dcn316_clk_mgr_construct()
645 clk_mgr->base.base.clks.ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz; in dcn316_clk_mgr_construct()
657 &clk_mgr->base, in dcn316_clk_mgr_construct()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
A Ddcn31_smu.c150 clk_mgr, in dcn31_smu_get_smu_version()
165 clk_mgr, in dcn31_smu_set_dispclk()
180 clk_mgr, in dcn31_smu_set_dprefclk()
200 clk_mgr, in dcn31_smu_set_hard_min_dcfclk()
218 clk_mgr, in dcn31_smu_set_min_deep_sleep_dcfclk()
233 clk_mgr, in dcn31_smu_set_dppclk()
250 clk_mgr, in dcn31_smu_set_display_idle_optimization()
268 clk_mgr, in dcn31_smu_enable_phy_refclk_pwrdwn()
279 clk_mgr, in dcn31_smu_enable_pme_wa()
343 clk_mgr, in dcn31_smu_set_zstate_support()
[all …]
A Ddcn31_clk_mgr.c55 clk_mgr->base.base.ctx->logger
296 void dcn31_init_clocks(struct clk_mgr *clk_mgr) in dcn31_init_clocks() argument
482 if (!clk_mgr->smu_ver) in dcn31_notify_wm_ranges()
504 if (!clk_mgr->smu_ver) in dcn31_get_dpm_table_from_smu()
686 clk_mgr->base.dccg = dccg; in dcn31_clk_mgr_construct()
695 clk_mgr->base.base.ctx, in dcn31_clk_mgr_construct()
707 clk_mgr->base.base.ctx, in dcn31_clk_mgr_construct()
719 clk_mgr->base.smu_ver = dcn31_smu_get_smu_version(&clk_mgr->base); in dcn31_clk_mgr_construct()
721 if (clk_mgr->base.smu_ver) in dcn31_clk_mgr_construct()
790 &clk_mgr->base, in dcn31_clk_mgr_construct()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
A Ddcn314_smu.c169 clk_mgr, in dcn314_smu_get_smu_version()
184 clk_mgr, in dcn314_smu_set_dispclk()
199 clk_mgr, in dcn314_smu_set_dprefclk()
219 clk_mgr, in dcn314_smu_set_hard_min_dcfclk()
237 clk_mgr, in dcn314_smu_set_min_deep_sleep_dcfclk()
252 clk_mgr, in dcn314_smu_set_dppclk()
269 clk_mgr, in dcn314_smu_set_display_idle_optimization()
287 clk_mgr, in dcn314_smu_enable_phy_refclk_pwrdwn()
298 clk_mgr, in dcn314_smu_enable_pme_wa()
382 clk_mgr, in dcn314_smu_set_zstate_support()
[all …]
A Ddcn314_clk_mgr.c58 clk_mgr->base.base.ctx->logger
184 void dcn314_init_clocks(struct clk_mgr *clk_mgr) in dcn314_init_clocks() argument
202 clk_mgr->dp_dto_source_clock_in_khz = clk_mgr->dprefclk_khz; in dcn314_init_clocks()
547 if (!clk_mgr->smu_ver) in dcn314_notify_wm_ranges()
569 if (!clk_mgr->smu_ver) in dcn314_get_dpm_table_from_smu()
797 clk_mgr->base.dccg = dccg; in dcn314_clk_mgr_construct()
806 clk_mgr->base.base.ctx, in dcn314_clk_mgr_construct()
818 clk_mgr->base.base.ctx, in dcn314_clk_mgr_construct()
830 clk_mgr->base.smu_ver = dcn314_smu_get_smu_version(&clk_mgr->base); in dcn314_clk_mgr_construct()
901 &clk_mgr->base, in dcn314_clk_mgr_construct()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn401/
A Ddcn401_fpu.c13 void dcn401_build_wm_range_table_fpu(struct clk_mgr *clk_mgr) in dcn401_build_wm_range_table_fpu() argument
32 …clk_mgr->bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->bw_params->clk_… in dcn401_build_wm_range_table_fpu()
34 if (clk_mgr->bw_params->clk_table.entries[2].memclk_mhz) in dcn401_build_wm_range_table_fpu()
38 clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid = true; in dcn401_build_wm_range_table_fpu()
50 clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid = true; in dcn401_build_wm_range_table_fpu()
73 …clk_mgr->bw_params->dummy_pstate_table[0].dram_speed_mts = clk_mgr->bw_params->clk_table.entries[0… in dcn401_build_wm_range_table_fpu()
75 …clk_mgr->bw_params->dummy_pstate_table[1].dram_speed_mts = clk_mgr->bw_params->clk_table.entries[1… in dcn401_build_wm_range_table_fpu()
77 …clk_mgr->bw_params->dummy_pstate_table[2].dram_speed_mts = clk_mgr->bw_params->clk_table.entries[2… in dcn401_build_wm_range_table_fpu()
79 …clk_mgr->bw_params->dummy_pstate_table[3].dram_speed_mts = clk_mgr->bw_params->clk_table.entries[3… in dcn401_build_wm_range_table_fpu()
85 …clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = clk_mgr->bw_params->du… in dcn401_build_wm_range_table_fpu()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
A Ddcn315_smu.c181 clk_mgr, in dcn315_smu_get_smu_version()
196 clk_mgr, in dcn315_smu_set_dispclk()
214 clk_mgr, in dcn315_smu_set_hard_min_dcfclk()
232 clk_mgr, in dcn315_smu_set_min_deep_sleep_dcfclk()
247 clk_mgr, in dcn315_smu_set_dppclk()
264 clk_mgr, in dcn315_smu_set_display_idle_optimization()
282 clk_mgr, in dcn315_smu_enable_phy_refclk_pwrdwn()
293 clk_mgr, in dcn315_smu_enable_pme_wa()
338 clk_mgr, in dcn315_smu_get_dpref_clk()
351 clk_mgr, in dcn315_smu_get_dtbclk()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
A Ddcn20_clk_mgr.c44 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
47 (clk_mgr->regs->reg)
109 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; in dcn20_update_clocks_update_dpp_dto()
343 void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr, in dcn2_update_clocks_fpga() argument
390 if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz) in dcn2_update_clocks_fpga()
391 clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz; in dcn2_update_clocks_fpga()
392 if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz) in dcn2_update_clocks_fpga()
393 clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz; in dcn2_update_clocks_fpga()
400 dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks); in dcn2_update_clocks_fpga()
403 void dcn2_init_clocks(struct clk_mgr *clk_mgr) in dcn2_init_clocks() argument
[all …]
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dclk_mgr.h274 void (*update_clocks)(struct clk_mgr *clk_mgr,
281 void (*set_low_power_state)(struct clk_mgr *clk_mgr);
282 void (*exit_low_power_state)(struct clk_mgr *clk_mgr);
283 bool (*is_ips_supported)(struct clk_mgr *clk_mgr);
285 void (*init_clocks)(struct clk_mgr *clk_mgr);
290 void (*enable_pme_wa) (struct clk_mgr *clk_mgr);
291 void (*get_clock)(struct clk_mgr *clk_mgr,
298 void (*notify_wm_ranges)(struct clk_mgr *clk_mgr);
310 void (*set_hard_max_memclk)(struct clk_mgr *clk_mgr);
320 bool (*is_smu_present)(struct clk_mgr *clk_mgr);
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/
A Ddcn201_clk_mgr.c43 (clk_mgr->regs->reg)
58 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
61 clk_mgr->base.ctx
75 static void dcn201_init_clocks(struct clk_mgr *clk_mgr) in dcn201_init_clocks() argument
180 struct clk_mgr_internal *clk_mgr, in dcn201_clk_mgr_construct() argument
186 clk_mgr->base.ctx = ctx; in dcn201_clk_mgr_construct()
188 clk_mgr->regs = &clk_mgr_regs; in dcn201_clk_mgr_construct()
192 clk_mgr->dccg = dccg; in dcn201_clk_mgr_construct()
194 clk_mgr->dfs_bypass_disp_clk = 0; in dcn201_clk_mgr_construct()
198 clk_mgr->ss_on_dprefclk = false; in dcn201_clk_mgr_construct()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
A Ddcn401_clk_mgr_smu_msg.c50 dcn401_smu_wait_for_response(clk_mgr, 10, 200000); in dcn401_smu_send_msg_with_param()
119 TRACE_SMU_MSG(msg_id, param_in, clk_mgr->base.ctx); in dcn401_smu_send_msg_with_param_delay()
138 dcn401_smu_send_msg_with_param(clk_mgr, in dcn401_smu_send_fclk_pstate_message()
146 dcn401_smu_send_msg_with_param(clk_mgr, in dcn401_smu_send_uclk_pstate_message()
162 dcn401_smu_send_msg_with_param(clk_mgr, in dcn401_smu_transfer_wm_table_dram_2_smu()
170 dcn401_smu_send_msg_with_param(clk_mgr, in dcn401_smu_set_pme_workaround()
230 dcn401_smu_send_msg_with_param(clk_mgr, in dcn401_smu_set_hard_min_by_freq()
251 dcn401_smu_send_msg_with_param(clk_mgr, in dcn401_smu_indicate_drr_status()
267 success = dcn401_smu_send_msg_with_param(clk_mgr, in dcn401_smu_set_idle_uclk_fclk_hardmin()
303 dcn401_smu_send_msg_with_param(clk_mgr, in dcn401_smu_set_min_deep_sleep_dcef_clk()
[all …]
A Ddcn401_clk_mgr.c44 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
47 (clk_mgr->regs->reg)
168 static void dcn401_build_wm_range_table(struct clk_mgr *clk_mgr) in dcn401_build_wm_range_table() argument
566 if (!clk_mgr->smu_present || !dcn401_is_ppclk_dpm_enabled(clk_mgr, clk)) in dcn401_set_hard_min_by_freq_optimized()
600 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz; in dcn401_update_clocks_update_dentist()
1469 dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32); in dcn401_notify_wm_ranges()
1661 clk_mgr->dccg = dccg; in dcn401_clk_mgr_construct()
1686 clk_mgr->base.clks.ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk; in dcn401_clk_mgr_construct()
1690 clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk; in dcn401_clk_mgr_construct()
1701 kfree(clk_mgr); in dcn401_clk_mgr_construct()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
A Drv1_clk_mgr.c34 static void rv1_init_clocks(struct clk_mgr *clk_mgr) in rv1_init_clocks() argument
44 bool cur_dpp_div = clk_mgr->base.clks.dispclk_khz > clk_mgr->base.clks.dppclk_khz; in rv1_determine_dppclk_threshold()
86 struct clk_mgr_internal *clk_mgr, in ramp_up_dispclk_with_dpp() argument
158 clk_mgr->funcs->set_dispclk(clk_mgr, dispclk_to_dpp_threshold); in ramp_up_dispclk_with_dpp()
159 clk_mgr->funcs->set_dprefclk(clk_mgr); in ramp_up_dispclk_with_dpp()
177 clk_mgr->funcs->set_dispclk(clk_mgr, new_clocks->dispclk_khz); in ramp_up_dispclk_with_dpp()
178 clk_mgr->funcs->set_dprefclk(clk_mgr); in ramp_up_dispclk_with_dpp()
202 ASSERT(clk_mgr->pp_smu); in rv1_update_clocks()
296 if (clk_mgr->pp_smu) { in rv1_enable_pme_wa()
321 clk_mgr->base.ctx = ctx; in rv1_clk_mgr_construct()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
A Drn_clk_mgr_vbios_smu.c137 clk_mgr, in rn_vbios_smu_get_smu_version()
151 clk_mgr, in rn_vbios_smu_set_dispclk()
172 clk_mgr, in rn_vbios_smu_set_dprefclk()
189 clk_mgr, in rn_vbios_smu_set_hard_min_dcfclk()
204 clk_mgr, in rn_vbios_smu_set_min_deep_sleep_dcfclk()
214 clk_mgr, in rn_vbios_smu_set_phyclk()
224 clk_mgr, in rn_vbios_smu_set_dppclk()
243 clk_mgr, in rn_vbios_smu_set_dcn_low_power_state()
251 clk_mgr, in rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn()
259 clk_mgr, in rn_vbios_smu_enable_pme_wa()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
A Ddcn301_smu.c153 clk_mgr, in dcn301_smu_set_dispclk()
167 clk_mgr, in dcn301_smu_set_dprefclk()
183 clk_mgr, in dcn301_smu_set_hard_min_dcfclk()
197 clk_mgr, in dcn301_smu_set_min_deep_sleep_dcfclk()
211 clk_mgr, in dcn301_smu_set_dppclk()
225 clk_mgr, in dcn301_smu_set_display_idle_optimization()
242 clk_mgr, in dcn301_smu_enable_phy_refclk_pwrdwn()
250 clk_mgr, in dcn301_smu_enable_pme_wa()
259 dcn301_smu_send_msg_with_param(clk_mgr, in dcn301_smu_set_dram_addr_high()
267 dcn301_smu_send_msg_with_param(clk_mgr, in dcn301_smu_set_dram_addr_low()
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A Dvg_clk_mgr.c55 #define TO_CLK_MGR_VGH(clk_mgr)\ argument
377 static void vg_init_clocks(struct clk_mgr *clk_mgr) in vg_init_clocks() argument
448 if (!clk_mgr->smu_ver) in vg_notify_wm_ranges()
646 if (!clk_mgr->smu_ver) in vg_get_dpm_table_from_smu()
675 clk_mgr->base.dccg = dccg; in vg_clk_mgr_construct()
684 clk_mgr->base.base.ctx, in vg_clk_mgr_construct()
696 clk_mgr->base.base.ctx, in vg_clk_mgr_construct()
708 clk_mgr->base.smu_ver = dcn301_smu_get_smu_version(&clk_mgr->base); in vg_clk_mgr_construct()
710 if (clk_mgr->base.smu_ver) in vg_clk_mgr_construct()
736 &clk_mgr->base, in vg_clk_mgr_construct()
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