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Searched refs:clk_mgr_internal (Results 1 – 25 of 64) sorted by relevance

123

/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
A Ddcn30_clk_mgr_smu_msg.h31 struct clk_mgr_internal;
33 bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input);
34 bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version);
35 bool dcn30_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr);
36 bool dcn30_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr);
37 void dcn30_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
38 void dcn30_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
39 void dcn30_smu_transfer_wm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
40 void dcn30_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
44 unsigned int dcn30_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk);
[all …]
A Ddcn30_clk_mgr_smu_msg.c112 bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input) in dcn30_smu_test_message()
126 bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version) in dcn30_smu_get_smu_version()
142 bool dcn30_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr) in dcn30_smu_check_driver_if_version()
161 bool dcn30_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr) in dcn30_smu_check_msg_header_version()
179 void dcn30_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high) in dcn30_smu_set_dram_addr_high()
187 void dcn30_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low) in dcn30_smu_set_dram_addr_low()
195 void dcn30_smu_transfer_wm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr) in dcn30_smu_transfer_wm_table_smu_2_dram()
203 void dcn30_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr) in dcn30_smu_transfer_wm_table_dram_2_smu()
279 unsigned int dcn30_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk) in dcn30_smu_get_dc_mode_max_dpm_freq()
304 void dcn30_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t num_displays) in dcn30_smu_set_num_of_displays()
[all …]
A Ddcn30_clk_mgr.c101 static void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr) in dcn3_build_wm_range_table()
110 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn3_init_clocks()
196 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn3_update_clocks()
326 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn3_notify_wm_ranges()
357 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn3_set_hard_min_memclk()
378 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn3_set_hard_max_memclk()
389 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn3_set_max_memclk()
398 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn3_set_min_memclk()
408 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn3_get_memclk_states_from_smu()
520 struct clk_mgr_internal *clk_mgr, in dcn3_clk_mgr_construct()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
A Ddcn35_smu.h179 int dcn35_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
181 int dcn35_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
184 int dcn35_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
187 void dcn35_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
190 void dcn35_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
191 void dcn35_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
194 void dcn35_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);
197 int dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr);
198 int dcn35_smu_get_ips_supported(struct clk_mgr_internal *clk_mgr);
199 int dcn35_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr);
[all …]
A Ddcn35_smu.c136 static int dcn35_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, in dcn35_smu_send_msg_with_param()
184 int dcn35_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) in dcn35_smu_get_smu_version()
210 int dcn35_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) in dcn35_smu_set_dprefclk()
313 void dcn35_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr) in dcn35_smu_enable_pme_wa()
343 void dcn35_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr) in dcn35_smu_transfer_dpm_table_smu_2_dram()
352 void dcn35_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr) in dcn35_smu_transfer_wm_table_dram_2_smu()
415 int dcn35_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr) in dcn35_smu_get_dprefclk()
430 int dcn35_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr) in dcn35_smu_get_dtbclk()
445 void dcn35_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable) in dcn35_smu_set_dtbclk()
469 int dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr) in dcn35_smu_exit_low_power_state()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
A Ddcn401_clk_mgr_smu_msg.h12 void dcn401_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support);
13 void dcn401_smu_send_uclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support);
14 void dcn401_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways);
15 void dcn401_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
16 void dcn401_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr);
18 void dcn401_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal *clk_mgr, bool enable);
19 void dcn401_smu_indicate_drr_status(struct clk_mgr_internal *clk_mgr, bool mod_drr_for_pstate);
20 bool dcn401_smu_set_idle_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,
23 bool dcn401_smu_set_active_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,
26 void dcn401_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz);
[all …]
A Ddcn401_clk_mgr_smu_msg.c134 void dcn401_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support) in dcn401_smu_send_fclk_pstate_message()
142 void dcn401_smu_send_uclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support) in dcn401_smu_send_uclk_pstate_message()
150 void dcn401_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways) in dcn401_smu_send_cab_for_uclk_message()
158 void dcn401_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr) in dcn401_smu_transfer_wm_table_dram_2_smu()
166 void dcn401_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr) in dcn401_smu_set_pme_workaround()
190 static bool dcn401_smu_wait_hard_min_status(struct clk_mgr_internal *clk_mgr, uint32_t ppclk) in dcn401_smu_wait_hard_min_status()
240 void dcn401_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal *clk_mgr, bool enable) in dcn401_smu_wait_for_dmub_ack_mclk()
247 void dcn401_smu_indicate_drr_status(struct clk_mgr_internal *clk_mgr, bool mod_drr_for_pstate) in dcn401_smu_indicate_drr_status()
255 bool dcn401_smu_set_idle_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr, in dcn401_smu_set_idle_uclk_fclk_hardmin()
277 bool dcn401_smu_set_active_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr, in dcn401_smu_set_active_uclk_fclk_hardmin()
[all …]
A Ddcn401_clk_mgr.c862 clk_mgr_internal, in dcn401_execute_block_sequence()
868 clk_mgr_internal, in dcn401_execute_block_sequence()
874 clk_mgr_internal, in dcn401_execute_block_sequence()
879 clk_mgr_internal, in dcn401_execute_block_sequence()
884 clk_mgr_internal, in dcn401_execute_block_sequence()
889 clk_mgr_internal, in dcn401_execute_block_sequence()
894 clk_mgr_internal, in dcn401_execute_block_sequence()
899 clk_mgr_internal, in dcn401_execute_block_sequence()
904 clk_mgr_internal, in dcn401_execute_block_sequence()
911 clk_mgr_internal, in dcn401_execute_block_sequence()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
A Ddcn315_smu.h114 int dcn315_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
115 int dcn315_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
118 int dcn315_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
120 void dcn315_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
122 void dcn315_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
123 void dcn315_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
124 void dcn315_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
126 void dcn315_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
127 int dcn315_smu_get_dpref_clk(struct clk_mgr_internal *clk_mgr);
128 int dcn315_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr);
[all …]
A Ddcn315_smu.c132 struct clk_mgr_internal *clk_mgr, in dcn315_smu_send_msg_with_param()
178 int dcn315_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) in dcn315_smu_get_smu_version()
187 int dcn315_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) in dcn315_smu_set_dispclk()
239 int dcn315_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz) in dcn315_smu_set_dppclk()
287 void dcn315_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr) in dcn315_smu_enable_pme_wa()
306 void dcn315_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low) in dcn315_smu_set_dram_addr_low()
315 void dcn315_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr) in dcn315_smu_transfer_dpm_table_smu_2_dram()
324 void dcn315_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr) in dcn315_smu_transfer_wm_table_dram_2_smu()
333 int dcn315_smu_get_dpref_clk(struct clk_mgr_internal *clk_mgr) in dcn315_smu_get_dpref_clk()
345 int dcn315_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr) in dcn315_smu_get_dtbclk()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
A Ddcn314_smu.h93 int dcn314_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
94 int dcn314_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
95 int dcn314_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
98 int dcn314_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
100 void dcn314_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
101 void dcn314_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
102 void dcn314_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
103 void dcn314_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
104 void dcn314_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
105 void dcn314_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
[all …]
A Ddcn314_smu.c119 static int dcn314_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, in dcn314_smu_send_msg_with_param()
166 int dcn314_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) in dcn314_smu_get_smu_version()
175 int dcn314_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) in dcn314_smu_set_dispclk()
191 int dcn314_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) in dcn314_smu_set_dprefclk()
244 int dcn314_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz) in dcn314_smu_set_dppclk()
274 void dcn314_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable) in dcn314_smu_enable_phy_refclk_pwrdwn()
292 void dcn314_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr) in dcn314_smu_enable_pme_wa()
312 void dcn314_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low) in dcn314_smu_set_dram_addr_low()
321 void dcn314_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr) in dcn314_smu_transfer_dpm_table_smu_2_dram()
330 void dcn314_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr) in dcn314_smu_transfer_wm_table_dram_2_smu()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
A Drn_clk_mgr_vbios_smu.h31 int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
32 int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
33 int rn_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
34 int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
35 int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_d…
36 void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz);
37 int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
38 void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, enum dcn_pwr_state);
39 void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
40 void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
[all …]
A Drn_clk_mgr_vbios_smu.c99 static int rn_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, in rn_vbios_smu_send_msg_with_param()
134 int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) in rn_vbios_smu_get_smu_version()
143 int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) in rn_vbios_smu_set_dispclk()
167 int rn_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) in rn_vbios_smu_set_dprefclk()
181 int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz) in rn_vbios_smu_set_hard_min_dcfclk()
211 void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz) in rn_vbios_smu_set_phyclk()
219 int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz) in rn_vbios_smu_set_dppclk()
233 void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, enum dcn_pwr_state stat… in rn_vbios_smu_set_dcn_low_power_state()
248 void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable) in rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn()
256 void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr) in rn_vbios_smu_enable_pme_wa()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
A Ddcn316_smu.h122 int dcn316_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
123 int dcn316_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
126 int dcn316_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
128 void dcn316_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
130 void dcn316_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
131 void dcn316_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
132 void dcn316_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
134 void dcn316_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
135 void dcn316_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);
136 int dcn316_smu_get_dpref_clk(struct clk_mgr_internal *clk_mgr);
[all …]
A Ddcn316_smu.c119 struct clk_mgr_internal *clk_mgr, in dcn316_smu_send_msg_with_param()
152 int dcn316_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) in dcn316_smu_get_smu_version()
161 int dcn316_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) in dcn316_smu_set_dispclk()
213 int dcn316_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz) in dcn316_smu_set_dppclk()
270 void dcn316_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low) in dcn316_smu_set_dram_addr_low()
279 void dcn316_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr) in dcn316_smu_transfer_dpm_table_smu_2_dram()
288 void dcn316_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr) in dcn316_smu_transfer_wm_table_dram_2_smu()
297 void dcn316_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr) in dcn316_smu_enable_pme_wa()
309 void dcn316_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable) in dcn316_smu_set_dtbclk()
320 int dcn316_smu_get_dpref_clk(struct clk_mgr_internal *clk_mgr) in dcn316_smu_get_dpref_clk()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
A Ddcn301_smu.h150 int dcn301_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
151 int dcn301_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
152 int dcn301_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
153 int dcn301_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
155 int dcn301_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
157 void dcn301_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
158 void dcn301_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
159 void dcn301_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
160 void dcn301_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
161 void dcn301_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
[all …]
A Ddcn301_smu.c98 static int dcn301_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, in dcn301_smu_send_msg_with_param()
133 int dcn301_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) in dcn301_smu_get_smu_version()
145 int dcn301_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) in dcn301_smu_set_dispclk()
160 int dcn301_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) in dcn301_smu_set_dprefclk()
204 int dcn301_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz) in dcn301_smu_set_dppclk()
230 void dcn301_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable) in dcn301_smu_enable_phy_refclk_pwrdwn()
247 void dcn301_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr) in dcn301_smu_enable_pme_wa()
255 void dcn301_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high) in dcn301_smu_set_dram_addr_high()
263 void dcn301_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low) in dcn301_smu_set_dram_addr_low()
271 void dcn301_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr) in dcn301_smu_transfer_dpm_table_smu_2_dram()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
A Ddcn31_smu.c103 static int dcn31_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, in dcn31_smu_send_msg_with_param()
147 int dcn31_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) in dcn31_smu_get_smu_version()
156 int dcn31_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) in dcn31_smu_set_dispclk()
172 int dcn31_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) in dcn31_smu_set_dprefclk()
225 int dcn31_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz) in dcn31_smu_set_dppclk()
255 void dcn31_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable) in dcn31_smu_enable_phy_refclk_pwrdwn()
273 void dcn31_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr) in dcn31_smu_enable_pme_wa()
293 void dcn31_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low) in dcn31_smu_set_dram_addr_low()
302 void dcn31_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr) in dcn31_smu_transfer_dpm_table_smu_2_dram()
311 void dcn31_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr) in dcn31_smu_transfer_wm_table_dram_2_smu()
[all …]
A Ddcn31_smu.h254 int dcn31_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
255 int dcn31_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
256 int dcn31_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
259 int dcn31_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
261 void dcn31_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
262 void dcn31_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
263 void dcn31_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
264 void dcn31_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
265 void dcn31_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
266 void dcn31_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
A Ddcn32_clk_mgr_smu_msg.h39 void dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable);
40 void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways);
41 void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
42 void dcn32_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr);
43 unsigned int dcn32_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_…
44 void dcn32_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal *clk_mgr, bool enable);
A Ddcn32_clk_mgr_smu_msg.c50 static uint32_t dcn32_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us… in dcn32_smu_wait_for_response()
71 static bool dcn32_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32… in dcn32_smu_send_msg_with_param()
160 void dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable) in dcn32_smu_send_fclk_pstate_message()
168 void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways) in dcn32_smu_send_cab_for_uclk_message()
176 void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr) in dcn32_smu_transfer_wm_table_dram_2_smu()
184 void dcn32_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr) in dcn32_smu_set_pme_workaround()
193 static bool dcn32_get_hard_min_status_supported(struct clk_mgr_internal *clk_mgr) in dcn32_get_hard_min_status_supported()
209 static unsigned int dcn32_smu_get_hard_min_status(struct clk_mgr_internal *clk_mgr, bool *no_timeou… in dcn32_smu_get_hard_min_status()
225 static bool dcn32_smu_wait_get_hard_min_status(struct clk_mgr_internal *clk_mgr, in dcn32_smu_wait_get_hard_min_status()
280 unsigned int dcn32_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_… in dcn32_smu_set_hard_min_by_freq()
[all …]
A Ddcn32_clk_mgr.h31 struct clk_mgr_internal *clk_mgr,
35 void dcn32_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
38 void dcn32_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr);
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/
A Ddce112_clk_mgr.h32 struct clk_mgr_internal *clk_mgr);
36 int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz);
37 int dce112_set_dprefclk(struct clk_mgr_internal *clk_mgr);
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/
A Dclk_mgr.c154 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create()
167 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create()
177 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create()
187 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create()
211 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create()
225 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create()
253 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create()
328 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create()
365 struct clk_mgr_internal *clk_mgr = dcn401_clk_mgr_construct(ctx, dccg); in dc_clk_mgr_create()
386 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dc_destroy_clk_mgr()

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