Searched refs:clock_div (Results 1 – 6 of 6) sorted by relevance
49 uint32_t clock_div = 0; in cvmx_helper_qlm_jtag_init() local54 clock_div++; in cvmx_helper_qlm_jtag_init()63 jtgc.s.clk_div = clock_div; in cvmx_helper_qlm_jtag_init()
1466 clock_div--; in cit_get_clock_div()1472 clock_div, fps[clock_div]); in cit_get_clock_div()1474 return clock_div; in cit_get_clock_div()1480 int clock_div; in cit_start_model0() local1841 clock_div = 6; in cit_start_model2()1847 clock_div = 8; in cit_start_model2()1855 clock_div = 10; in cit_start_model2()1862 clock_div = 16; in cit_start_model2()2045 clock_div = 3; in cit_start_model3()2069 clock_div = 5; in cit_start_model3()[all …]
267 uint clock_div = 0; in stm32_rng_clock_freq_restrain() local276 while ((clock_rate >> clock_div) > priv->data->max_clock_rate) in stm32_rng_clock_freq_restrain()277 clock_div++; in stm32_rng_clock_freq_restrain()279 pr_debug("RNG clk rate : %lu\n", clk_get_rate(priv->clk) >> clock_div); in stm32_rng_clock_freq_restrain()281 return clock_div; in stm32_rng_clock_freq_restrain()305 uint clock_div = stm32_rng_clock_freq_restrain(rng); in stm32_rng_init() local309 (clock_div << RNG_CR_CLKDIV_SHIFT); in stm32_rng_init()
265 u32 clock_div; in pci1xxxx_rs485_config() local286 clock_div = readl(port->membase + UART_BAUD_CLK_DIVISOR_REG); in pci1xxxx_rs485_config()288 FIELD_GET(BAUD_CLOCK_DIV_INT_MSK, clock_div) * in pci1xxxx_rs485_config()
411 u_char clock_div; member501 cyber2000_grphw(EXT_DCLK_DIV, hw->clock_div, cfb); in cyber2000fb_set_timing()733 hw->clock_div = div2 << 6 | (best_div1 - 1); in cyber2000fb_decode_clock()738 hw->clock_div |= EXT_DCLK_DIV_VFSEL; in cyber2000fb_decode_clock()
387 u8 clock_div; /* Clock divider */ member
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