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/linux/Documentation/admin-guide/
A Dlockup-watchdogs.rst67 By default, the watchdog runs on all online cores. However, on a
69 on the housekeeping cores, not the cores specified in the "nohz_full"
71 the "nohz_full" cores, we would have to run timer ticks to activate
73 from protecting the user code on those cores from the kernel.
74 Of course, disabling it by default on the nohz_full cores means that
75 when those cores do enter the kernel, by default we will not be
77 to continue to run on the housekeeping (non-tickless) cores means
78 that we will continue to detect lockups properly on those cores.
80 In either case, the set of cores excluded from running the watchdog
82 nohz_full cores, this may be useful for debugging a case where the
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/linux/drivers/gpu/drm/nouveau/dispnv50/
A Dcore.c44 } cores[] = { in nv50_core_new() local
66 cid = nvif_mclass(&disp->disp->object, cores); in nv50_core_new()
72 return cores[cid].new(drm, cores[cid].oclass, pcore); in nv50_core_new()
/linux/Documentation/devicetree/bindings/timer/
A Dsnps,arc-timer.txt4 - Two identical copies TIMER0 and TIMER1 exist in ARC cores and historically
5 TIMER0 used as clockevent provider (true for all ARC cores)
12 (16 for ARCHS cores, 3 for ARC700 cores)
/linux/Documentation/networking/device_drivers/can/freescale/
A Dflexcan.rst13 For most flexcan IP cores the driver supports 2 RX modes:
18 The older flexcan cores (integrated into the i.MX25, i.MX28, i.MX35
28 cores come up in a mode where RTR reception is possible.
39 On some IP cores the controller cannot receive RTR frames in the
45 Waive ability to receive RTR frames. (not supported on all IP cores)
48 some IP cores RTR frames cannot be received anymore.
/linux/drivers/remoteproc/
A Dti_k3_r5_remoteproc.c112 struct list_head cores; member
300 list_for_each_entry(core, &cluster->cores, elem) { in k3_r5_lockstep_reset()
311 list_for_each_entry(core, &cluster->cores, elem) { in k3_r5_lockstep_reset()
345 list_for_each_entry_reverse(core, &cluster->cores, elem) { in k3_r5_lockstep_release()
357 list_for_each_entry_reverse(core, &cluster->cores, elem) { in k3_r5_lockstep_release()
375 list_for_each_entry_from(core, &cluster->cores, elem) { in k3_r5_lockstep_release()
637 list_for_each_entry(core, &cluster->cores, elem) { in k3_r5_rproc_stop()
926 list_for_each_entry(temp, &cluster->cores, elem) { in k3_r5_rproc_configure()
1230 list_for_each_entry(core, &cluster->cores, elem) { in k3_r5_cluster_rproc_init()
1686 list_add_tail(&core->elem, &cluster->cores); in k3_r5_cluster_of_init()
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/linux/Documentation/devicetree/bindings/media/xilinx/
A Dvideo.txt1 DT bindings for Xilinx video IP cores
4 Xilinx video IP cores process video streams by acting as video sinks and/or
10 cores are represented as defined in ../video-interfaces.txt.
18 The following properties are common to all Xilinx video IP cores.
21 AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream
A Dxlnx,video.txt8 video IP cores. Each video IP core is represented as documented in video.txt
11 mappings between DMAs and the video IP cores.
/linux/drivers/net/can/esd/
A Desd_402_pci-core.c50 struct acc_core *cores; member
103 irq_status = acc_card_interrupt(&card->ov, card->cores); in pci402_interrupt()
195 card->cores = devm_kcalloc(&pdev->dev, card->ov.active_cores, in pci402_init_card()
197 if (!card->cores) in pci402_init_card()
286 acc_init_bm_ptr(&card->ov, card->cores, card->dma_buf); in pci402_init_dma()
316 struct acc_core *core = &card->cores[i]; in pci402_finish_dma()
343 struct acc_core *core = &card->cores[i]; in pci402_init_cores()
404 pci402_unregister_core(&card->cores[i]); in pci402_init_cores()
415 pci402_unregister_core(&card->cores[i]); in pci402_finish_cores()
/linux/Documentation/devicetree/bindings/bus/
A Dbrcm,bus-axi.txt9 The cores on the AXI bus are automatically detected by bcma with the
12 BCM47xx/BCM53xx ARM SoCs. To assign IRQ numbers to the cores, provide
17 The top-level axi bus may contain children representing attached cores
19 detected (e.g. IRQ numbers). Also some of the cores may be responsible
/linux/arch/x86/kernel/cpu/
A Dtopology_common.c50 unsigned int cores, core_shift, smt_shift = 0; in parse_legacy() local
53 cores = parse_num_cores_legacy(c); in parse_legacy()
54 core_shift = get_count_order(cores); in parse_legacy()
65 cores <<= smt_shift; in parse_legacy()
69 topology_set_dom(tscan, TOPO_CORE_DOMAIN, core_shift, cores); in parse_legacy()
/linux/Documentation/devicetree/bindings/remoteproc/
A Dti,pru-consumer.yaml37 firmwares for the PRU cores, the default firmware for the core from
39 correspond to the PRU cores listed in the 'ti,prus' property
50 should correspond to the PRU cores listed in the 'ti,prus' property. The
52 and Tx_PRU0 on K3 SoCs). Use the same value for all cores within the
A Dmtk,scp.yaml88 The other cores are represented as child nodes of the boot core.
94 cores. The power of cache, SRAM and L1TCM power should be enabled
95 before booting SCP cores. The size of cache, SRAM, and L1TCM are varied
98 The SCP cores do not use an MMU, but has a set of registers to
123 initializing sub cores of multi-core SCP.
/linux/Documentation/devicetree/bindings/arm/
A Darm,vexpress-juno.yaml45 - description: CoreTile Express A9x4 (V2P-CA9) has 4 Cortex A9 CPU cores
51 - description: CoreTile Express A5x2 (V2P-CA5s) has 2 Cortex A5 CPU cores
58 cores in a MPCore configuration in a test chip on the core tile. See
64 A15 CPU cores in a test chip on the core tile. This is the first test
71 CPU cores and 3 Cortex A7 cores in a big.LITTLE MPCore configuration
77 cores in a test chip on the core tile. See ARM DDI 0498D.
84 AArch64 CPU cores. It has 2 Cortex A57 CPU cores and 4 Cortex A53
85 cores in a big.LITTLE configuration. It also features the MALI T624
/linux/arch/x86/mm/
A Damdtopology.c58 unsigned int numnodes, cores, apicid; in amd_numa_init() local
163 cores = topology_get_domain_size(TOPO_CORE_DOMAIN); in amd_numa_init()
170 for (j = 0; j < cores; j++, apicid++) in amd_numa_init()
/linux/arch/riscv/
A DKconfig.errata9 here if your platform uses Andes CPU cores.
20 non-standard handling on non-coherent operations on Andes cores.
30 here if your platform uses SiFive CPU cores.
81 here if your platform uses T-HEAD CPU cores.
114 The T-Head C9xx cores implement a PMU overflow extension very
/linux/drivers/bcma/
A Dmain.c92 list_for_each_entry(core, &bus->cores, list) { in bcma_find_core_unit()
272 INIT_LIST_HEAD(&bus->cores); in bcma_init_bus()
296 list_for_each_entry(core, &bus->cores, list) { in bcma_register_devices()
366 list_for_each_entry_safe(core, tmp, &bus->cores, list) { in bcma_unregister_cores()
376 list_for_each_entry_safe(core, tmp, &bus->cores, list) { in bcma_unregister_cores()
412 list_for_each_entry(core, &bus->cores, list) { in bcma_bus_register()
537 list_for_each_entry(core, &bus->cores, list) { in bcma_bus_suspend()
558 list_for_each_entry(core, &bus->cores, list) { in bcma_bus_resume()
/linux/sound/soc/sof/
A Dipc4-mtrace.c113 struct sof_mtrace_core_data cores[]; member
403 debugfs_create_file(dfs_name, 0444, dfs_root, &priv->cores[i], in mtrace_debugfs_create()
483 struct sof_mtrace_core_data *core_data = &priv->cores[i]; in ipc4_mtrace_disable()
519 core_data = &priv->cores[core]; in sof_mtrace_find_core_slots()
556 priv = devm_kzalloc(sdev->dev, struct_size(priv, cores, sdev->num_cores), in ipc4_mtrace_init()
570 struct sof_mtrace_core_data *core_data = &priv->cores[i]; in ipc4_mtrace_init()
625 core_data = &priv->cores[core]; in sof_ipc4_mtrace_update_pos()
/linux/drivers/gpu/drm/v3d/
A Dv3d_irq.c224 for (core = 0; core < v3d->cores; core++) in v3d_irq_init()
269 for (core = 0; core < v3d->cores; core++) { in v3d_irq_enable()
284 for (core = 0; core < v3d->cores; core++) in v3d_irq_disable()
289 for (core = 0; core < v3d->cores; core++) in v3d_irq_disable()
A Dv3d_debugfs.c119 for (core = 0; core < v3d->cores; core++) { in v3d_v3d_debugfs_regs()
149 u32 ident0, ident1, ident2, ident3, cores; in v3d_v3d_debugfs_ident() local
156 cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES); in v3d_v3d_debugfs_ident()
177 for (core = 0; core < cores; core++) { in v3d_v3d_debugfs_ident()
/linux/drivers/net/wireless/intel/iwlwifi/tests/
A Ddevinfo.c19 di->cores); in iwl_pci_print_dev_info()
34 di->no_160, di->cores, di->rf_step); in devinfo_table_order()
/linux/arch/arm64/boot/dts/qcom/
A Dsdm632.dtsi45 * CPU0-3 are efficiency cores, CPU4-7 are performance cores
/linux/Documentation/ABI/testing/
A Dsysfs-bus-bcma14 There are a few types of BCMA cores, they can be identified by
22 BCMA cores of the same type can still slightly differ depending
/linux/arch/arm/boot/dts/arm/
A Dvexpress-v2p-ca15-tc1.dts199 regulator-cores {
210 amp-cores {
211 /* Total current for the two cores */
224 power-cores {
/linux/Documentation/admin-guide/device-mapper/
A Dunstriped.rst85 Intel NVMe drives contain two cores on the physical device.
88 in a 256k stripe across the two cores::
100 are striped across the two cores. When we unstripe this hardware RAID 0
113 unstriped on top of Intel NVMe device that has 2 cores
/linux/Documentation/locking/
A Dpercpu-rw-semaphore.rst9 cores take the lock for reading, the cache line containing the semaphore
10 is bouncing between L1 caches of the cores, causing performance

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