| /linux/drivers/gpu/drm/amd/amdkfd/ |
| A D | kfd_mqd_manager_cik.c | 179 m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE | in __update_mqd()
183 m->cp_hqd_pq_control |= PQ_ATC_EN; in __update_mqd()
191 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; in __update_mqd()
201 m->cp_hqd_pq_control |= NO_UPDATE_RPTR; in __update_mqd()
342 m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE | in update_mqd_hiq()
351 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; in update_mqd_hiq()
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| A D | kfd_mqd_manager_v12.c | 187 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; in update_mqd()
188 m->cp_hqd_pq_control |= in update_mqd()
190 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; in update_mqd()
191 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); in update_mqd()
229 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | in update_mqd()
298 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
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| A D | kfd_mqd_manager_v10.c | 170 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; in update_mqd()
171 m->cp_hqd_pq_control |= in update_mqd()
173 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; in update_mqd()
174 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); in update_mqd()
212 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | in update_mqd()
318 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
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| A D | kfd_mqd_manager_v11.c | 224 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; in update_mqd()
225 m->cp_hqd_pq_control |= in update_mqd()
227 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; in update_mqd()
228 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); in update_mqd()
266 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | in update_mqd()
372 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
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| A D | kfd_mqd_manager_v9.c | 247 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; in update_mqd()
248 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; in update_mqd()
249 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); in update_mqd()
293 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | in update_mqd()
428 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
549 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | in init_mqd_hiq_v9_4_3()
558 m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK; in init_mqd_hiq_v9_4_3()
693 m->cp_hqd_pq_control &= in init_mqd_v9_4_3()
731 m->cp_hqd_pq_control &= in update_mqd_v9_4_3()
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| A D | kfd_mqd_manager_vi.c | 178 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT | in __update_mqd()
181 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; in __update_mqd()
182 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); in __update_mqd()
225 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | in __update_mqd()
329 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
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| /linux/drivers/gpu/drm/amd/include/ |
| A D | cik_structs.h | 96 uint32_t cp_hqd_pq_control; member
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| A D | vi_structs.h | 305 uint32_t cp_hqd_pq_control; member
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| A D | v9_structs.h | 315 uint32_t cp_hqd_pq_control; member
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| A D | v11_structs.h | 820 uint32_t cp_hqd_pq_control; // offset: 145 (0x91) member
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| A D | v12_structs.h | 820 uint32_t cp_hqd_pq_control; // offset: 145 (0x91) member
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| A D | v10_structs.h | 821 uint32_t cp_hqd_pq_control; member
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_amdkfd_gc_9_4_3.c | 329 2 << REG_GET_FIELD(m->cp_hqd_pq_control, in kgd_gfx_v9_4_3_hqd_load()
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| A D | gfx_v7_0.c | 2853 mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL); in gfx_v7_0_mqd_init()
2854 mqd->cp_hqd_pq_control &= in gfx_v7_0_mqd_init()
2858 mqd->cp_hqd_pq_control |= in gfx_v7_0_mqd_init()
2860 mqd->cp_hqd_pq_control |= in gfx_v7_0_mqd_init()
2863 mqd->cp_hqd_pq_control |= in gfx_v7_0_mqd_init()
2866 mqd->cp_hqd_pq_control &= in gfx_v7_0_mqd_init()
2870 mqd->cp_hqd_pq_control |= in gfx_v7_0_mqd_init()
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| A D | amdgpu_amdkfd_gfx_v10_3.c | 240 2 << REG_GET_FIELD(m->cp_hqd_pq_control, in hqd_load_v10_3()
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| A D | amdgpu_amdkfd_gfx_v11.c | 225 2 << REG_GET_FIELD(m->cp_hqd_pq_control, in hqd_load_v11()
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| A D | mes_v12_0.c | 1066 mqd->cp_hqd_pq_control = tmp; in mes_v12_0_mqd_init()
1148 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); in mes_v12_0_queue_init_register()
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| A D | mes_v11_0.c | 1100 mqd->cp_hqd_pq_control = tmp; in mes_v11_0_mqd_init()
1175 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); in mes_v11_0_queue_init_register()
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| A D | amdgpu_amdkfd_gfx_v10.c | 254 2 << REG_GET_FIELD(m->cp_hqd_pq_control, in kgd_hqd_load()
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| A D | amdgpu_amdkfd_gfx_v9.c | 268 2 << REG_GET_FIELD(m->cp_hqd_pq_control, in kgd_gfx_v9_hqd_load()
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| A D | gfx_v9_4_3.c | 1883 mqd->cp_hqd_pq_control = tmp; in gfx_v9_4_3_xcc_mqd_init()
1984 mqd->cp_hqd_pq_control); in gfx_v9_4_3_xcc_kiq_init_register()
2093 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) { in gfx_v9_4_3_xcc_kiq_init_queue()
2138 if (!restore && (!tmp_mqd->cp_hqd_pq_control || in gfx_v9_4_3_xcc_kcq_init_queue()
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| A D | gfx_v9_0.c | 3562 mqd->cp_hqd_pq_control = tmp; in gfx_v9_0_mqd_init()
3662 mqd->cp_hqd_pq_control); in gfx_v9_0_kiq_init_register()
3771 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control){ in gfx_v9_0_kiq_init_queue()
3817 if (!restore && (!tmp_mqd->cp_hqd_pq_control || in gfx_v9_0_kcq_init_queue()
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| A D | gfx_v12_0.c | 3065 mqd->cp_hqd_pq_control = tmp; in gfx_v12_0_compute_mqd_init()
3182 mqd->cp_hqd_pq_control); in gfx_v12_0_kiq_init_register()
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| A D | gfx_v11_0.c | 4121 mqd->cp_hqd_pq_control = tmp; in gfx_v11_0_compute_mqd_init()
4238 mqd->cp_hqd_pq_control); in gfx_v11_0_kiq_init_register()
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| /linux/drivers/gpu/drm/radeon/ |
| A D | cik.c | 4451 u32 cp_hqd_pq_control; member
4658 mqd->queue_state.cp_hqd_pq_control = RREG32(CP_HQD_PQ_CONTROL); in cik_cp_compute_resume()
4659 mqd->queue_state.cp_hqd_pq_control &= in cik_cp_compute_resume()
4662 mqd->queue_state.cp_hqd_pq_control |= in cik_cp_compute_resume()
4664 mqd->queue_state.cp_hqd_pq_control |= in cik_cp_compute_resume()
4667 mqd->queue_state.cp_hqd_pq_control |= BUF_SWAP_32BIT; in cik_cp_compute_resume()
4669 mqd->queue_state.cp_hqd_pq_control &= in cik_cp_compute_resume()
4671 mqd->queue_state.cp_hqd_pq_control |= in cik_cp_compute_resume()
4673 WREG32(CP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control); in cik_cp_compute_resume()
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