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/linux/drivers/staging/vme_user/
A Dvme_fake.c213 bridge->slaves[i].cycle = cycle; in fake_slave_set()
241 *cycle = bridge->slaves[i].cycle; in fake_slave_get()
321 bridge->masters[i].cycle = cycle; in fake_master_set()
352 *cycle = bridge->masters[i].cycle; in __fake_master_get()
429 if (cycle != bridge->slaves[i].cycle) in fake_vmeread8()
459 if (cycle != bridge->slaves[i].cycle) in fake_vmeread16()
492 if (cycle != bridge->slaves[i].cycle) in fake_vmeread32()
532 cycle = priv->masters[i].cycle; in fake_master_read()
622 if (cycle != bridge->slaves[i].cycle) in fake_vmewrite8()
721 cycle = bridge->masters[i].cycle; in fake_master_write()
[all …]
A Dvme_tsi148.c568 if (cycle & VME_BLT) in tsi148_slave_set()
650 *cycle = 0; in tsi148_slave_get()
683 *cycle |= VME_BLT; in tsi148_slave_get()
685 *cycle |= VME_MBLT; in tsi148_slave_get()
696 *cycle |= VME_USER; in tsi148_slave_get()
698 *cycle |= VME_PROG; in tsi148_slave_get()
700 *cycle |= VME_DATA; in tsi148_slave_get()
1075 *cycle = 0; in __tsi148_master_get()
1111 *cycle |= VME_SCT; in __tsi148_master_get()
1113 *cycle |= VME_BLT; in __tsi148_master_get()
[all …]
A Dvme.c137 u32 aspace, cycle, dwidth; in vme_get_size() local
252 u32 cycle) in vme_slave_request() argument
276 ((slave_image->cycle_attr & cycle) == cycle) && in vme_slave_request()
348 ((image->cycle_attr & cycle) == cycle))) { in vme_slave_set()
358 aspace, cycle); in vme_slave_set()
397 aspace, cycle); in vme_slave_get()
470 ((master_image->cycle_attr & cycle) == cycle) && in vme_master_request()
545 ((image->cycle_attr & cycle) == cycle) && in vme_master_set()
556 cycle, dwidth); in vme_master_set()
595 cycle, dwidth); in vme_master_get()
[all …]
/linux/drivers/ata/
A Dlibata-pata-timings.c70 q->cycle = EZ(t->cycle, T); in ata_timing_quantize()
92 m->cycle = max(a->cycle, b->cycle); in ata_timing_merge()
141 p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO]; in ata_timing_compute()
144 p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO_IORDY]; in ata_timing_compute()
146 p.cycle = id[ATA_ID_EIDE_DMA_MIN]; in ata_timing_compute()
177 if (t->active + t->recover < t->cycle) { in ata_timing_compute()
178 t->active += (t->cycle - (t->active + t->recover)) / 2; in ata_timing_compute()
179 t->recover = t->cycle - t->active; in ata_timing_compute()
187 if (t->active + t->recover > t->cycle) in ata_timing_compute()
188 t->cycle = t->active + t->recover; in ata_timing_compute()
A Dpata_icside.c192 unsigned int cycle; in pata_icside_set_dmamode() local
205 if (t.active <= 50 && t.recover <= 375 && t.cycle <= 425) { in pata_icside_set_dmamode()
207 cycle = 187; in pata_icside_set_dmamode()
208 } else if (t.active <= 125 && t.recover <= 375 && t.cycle <= 500) { in pata_icside_set_dmamode()
210 cycle = 250; in pata_icside_set_dmamode()
211 } else if (t.active <= 200 && t.recover <= 550 && t.cycle <= 750) { in pata_icside_set_dmamode()
213 cycle = 437; in pata_icside_set_dmamode()
216 cycle = 562; in pata_icside_set_dmamode()
220 t.active, t.recover, t.cycle, iomd_type); in pata_icside_set_dmamode()
222 state->port[ap->port_no].speed[adev->devno] = cycle; in pata_icside_set_dmamode()
/linux/arch/alpha/lib/
A Dev6-csum_ipv6_magic.S116 cmpult $20,$3,$3 # E : (1 cycle stall on $20)
117 addq $20,$18,$20 # E : U L U L (1 cycle stall on $20)
120 addq $20,$19,$20 # E : (1 cycle stall on $20)
125 addq $18,$19,$18 # E : (1 cycle stall on $19)
131 zapnot $0,15,$1 # U : Start folding output (1 cycle stall on $0)
133 srl $0,32,$0 # U : U L U L : (1 cycle stall on $0)
136 extwl $1,2,$2 # U : ushort[1] (1 cycle stall on $1)
137 zapnot $1,3,$0 # U : ushort[0] (1 cycle stall on $1)
138 extwl $1,4,$1 # U : ushort[2] (1 cycle stall on $1)
143 extwl $3,2,$1 # U : ushort[1] (1 cycle stall on $3)
[all …]
/linux/scripts/
A Dheaderdep.pl116 my $cycle = shift;
119 for my $i (0 .. $#$cycle - 1) {
120 $cycle->[$i]->[0] = $cycle->[$i + 1]->[0];
122 $cycle->[-1]->[0] = 0;
124 my $first = shift @$cycle;
125 my $last = pop @$cycle;
130 for my $header (reverse @$cycle) {
/linux/kernel/locking/
A Dtest-ww_mutex.c288 struct test_cycle *cycle = container_of(work, typeof(*cycle), work); in test_cycle_work() local
293 ww_mutex_lock(&cycle->a_mutex, &ctx); in test_cycle_work()
295 complete(cycle->a_signal); in test_cycle_work()
301 ww_mutex_unlock(&cycle->a_mutex); in test_cycle_work()
307 ww_mutex_unlock(cycle->b_mutex); in test_cycle_work()
309 ww_mutex_unlock(&cycle->a_mutex); in test_cycle_work()
312 cycle->result = err ?: erra; in test_cycle_work()
338 init_completion(&cycle->b_signal); in __test_cycle()
341 cycle->result = 0; in __test_cycle()
353 if (!cycle->result) in __test_cycle()
[all …]
/linux/drivers/clocksource/
A Dtimer-atmel-pit.c43 u32 cycle; member
85 elapsed += PIT_PICNT(t) * data->cycle; in read_pit_clk()
95 pit_write(data->base, AT91_PIT_MR, (data->cycle - 1) | AT91_PIT_PITEN); in pit_clkevt_shutdown()
107 data->cnt += data->cycle * PIT_PICNT(pit_read(data->base, AT91_PIT_PIVR)); in pit_clkevt_set_periodic()
109 (data->cycle - 1) | AT91_PIT_PITEN | AT91_PIT_PITIEN); in pit_clkevt_set_periodic()
132 (data->cycle - 1) | AT91_PIT_PITEN); in at91sam926x_pit_reset()
153 data->cnt += data->cycle * PIT_PICNT(pit_read(data->base, in at91sam926x_pit_interrupt()
210 data->cycle = DIV_ROUND_CLOSEST(pit_rate, HZ); in at91sam926x_pit_dt_init()
211 WARN_ON(((data->cycle - 1) & ~AT91_PIT_PIV) != 0); in at91sam926x_pit_dt_init()
220 bits = 12 /* PICNT */ + ilog2(data->cycle) /* PIV */; in at91sam926x_pit_dt_init()
/linux/Documentation/devicetree/bindings/input/
A Dpwm-vibrator.yaml14 strength increases based on the duty cycle of the enable PWM channel
15 (100% duty cycle meaning strongest vibration, 0% meaning no vibration).
18 driven at fixed duty cycle. If available this is can be used to increase
39 direction-duty-cycle-ns:
41 Duty cycle of the direction PWM channel in nanoseconds,
58 direction-duty-cycle-ns = <1000000000>;
/linux/tools/power/cpupower/bench/
A Dbenchmark.c80 unsigned int _round, cycle; in start_benchmark() local
125 for (cycle = 0; cycle < config->cycles; cycle++) { in start_benchmark()
151 for (cycle = 0; cycle < config->cycles; cycle++) { in start_benchmark()
/linux/drivers/pwm/
A Dpwm-sl28cpld.c129 unsigned int cycle, prescaler; in sl28cpld_pwm_apply() local
152 cycle = SL28CPLD_PWM_FROM_DUTY_CYCLE(state->duty_cycle); in sl28cpld_pwm_apply()
153 cycle = min_t(unsigned int, cycle, SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler)); in sl28cpld_pwm_apply()
163 if (cycle == SL28CPLD_PWM_MAX_DUTY_CYCLE(0)) { in sl28cpld_pwm_apply()
166 cycle = SL28CPLD_PWM_MAX_DUTY_CYCLE(1); in sl28cpld_pwm_apply()
181 ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CYCLE, cycle); in sl28cpld_pwm_apply()
191 ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CYCLE, cycle); in sl28cpld_pwm_apply()
/linux/sound/firewire/
A Damdtp-stream.c899 cycle += addend; in increment_ohci_cycle_count()
902 return cycle; in increment_ohci_cycle_count()
951 unsigned int cycle; in generate_tx_packet_descs() local
987 next_cycle, cycle); in generate_tx_packet_descs()
997 desc->cycle = cycle; in generate_tx_packet_descs()
1106 latest_cycle = desc->cycle; in compute_pcm_extra_delay()
1249 unsigned int cycle; in skip_rx_packets() local
1384 unsigned int cycle; in drop_tx_packets() local
1538 if (cycle == UINT_MAX || in drop_tx_packets_initially()
1540 cycle = next_cycle; in drop_tx_packets_initially()
[all …]
/linux/Documentation/devicetree/bindings/regulator/
A Dpwm-regulator.yaml19 duty-cycle values must be provided via DT. Limitations are that the
21 Intermediary duty-cycle values which would normally allow finer grained
29 appropriate duty-cycle values. This allows for a much more fine grained
31 make an assumption that a %50 duty-cycle value will cause the regulator
54 - description: duty-cycle in percent (%)
63 Integer value encoding the duty cycle unit. If not
75 Duty cycle values are expressed in pwm-dutycycle-unit.
104 * Inverted PWM logic, and the duty cycle range is limited
/linux/Documentation/admin-guide/perf/
A Dalibaba_pmu.rst27 pmu_cycle_cnt_low and pmu_cycle_cnt_high, that is used as the cycle count
61 -e ali_drw_21000/cycle/ \
65 -e ali_drw_21080/cycle/ \
69 -e ali_drw_23000/cycle/ \
73 -e ali_drw_23080/cycle/ \
77 -e ali_drw_25000/cycle/ \
81 -e ali_drw_25080/cycle/ \
85 -e ali_drw_27000/cycle/ \
89 -e ali_drw_27080/cycle/ -- sleep 10
/linux/arch/mips/dec/
A Dkn02xa-berr.c53 const char *kind, *agent, *cycle, *event; in dec_kn02xa_be_backend() local
72 cycle = mreadstr; in dec_kn02xa_be_backend()
75 cycle = invoker ? writestr : readstr; in dec_kn02xa_be_backend()
84 kind, agent, cycle, event, address); in dec_kn02xa_be_backend()
A Dkn01-berr.c81 const char *kind, *agent, *cycle, *event; in dec_kn01_be_backend() local
126 cycle = mreadstr; in dec_kn01_be_backend()
129 cycle = invoker ? writestr : readstr; in dec_kn01_be_backend()
138 kind, agent, cycle, event, address); in dec_kn01_be_backend()
/linux/Documentation/hwmon/
A Ddme1737.rst199 pwm[1-3]_auto_point1_pwm low-speed duty-cycle
200 pwm[1-3]_auto_pwm_min min-speed duty-cycle
215 all PWM outputs are set to 100% duty-cycle.
228 duty-cycle >
288 to full-speed (100% duty-cycle).
320 fast the PWM duty-cycle will change
325 cycle changes instantly).
336 cycle. Supported values are 0 or
339 low-speed duty-cycle.
341 full-speed duty-cycle which is hard-
[all …]
A Dvt1211.rst196 pwm[1-2]_auto_point4_pwm full speed duty-cycle (hard-wired to 255)
197 pwm[1-2]_auto_point3_pwm high speed duty-cycle
198 pwm[1-2]_auto_point2_pwm low speed duty-cycle
199 pwm[1-2]_auto_point1_pwm off duty-cycle (hard-wired to 0)
212 PWM output duty-cycle based on the input temperature:
218 - full speed duty-cycle full speed duty-cycle
220 - high speed duty-cycle full speed duty-cycle
222 - low speed duty-cycle high speed duty-cycle
224 - off duty-cycle low speed duty-cycle
/linux/Documentation/devicetree/bindings/spi/
A Drenesas,sh-msiof.yaml119 - 50 # 0.5-clock-cycle delay
120 - 100 # 1-clock-cycle delay
121 - 150 # 1.5-clock-cycle delay
122 - 200 # 2-clock-cycle delay
129 - 50 # 0.5-clock-cycle delay
130 - 100 # 1-clock-cycle delay
131 - 150 # 1.5-clock-cycle delay
132 - 200 # 2-clock-cycle delay
133 - 300 # 3-clock-cycle delay
/linux/drivers/mfd/
A Datmel-smc.c229 conf->cycle &= ~GENMASK(shift + 15, shift); in atmel_smc_cs_conf_set_cycle()
230 conf->cycle |= val << shift; in atmel_smc_cs_conf_set_cycle()
250 regmap_write(regmap, ATMEL_SMC_CYCLE(cs), conf->cycle); in atmel_smc_cs_conf_apply()
271 regmap_write(regmap, ATMEL_HSMC_CYCLE(layout, cs), conf->cycle); in atmel_hsmc_cs_conf_apply()
291 regmap_read(regmap, ATMEL_SMC_CYCLE(cs), &conf->cycle); in atmel_smc_cs_conf_get()
312 regmap_read(regmap, ATMEL_HSMC_CYCLE(layout, cs), &conf->cycle); in atmel_hsmc_cs_conf_get()
/linux/fs/bcachefs/
A Dbtree_locking.c192 if (cycle) { in break_cycle()
193 print_cycle(cycle, g); in break_cycle()
238 struct printbuf *cycle) in lock_graph_descend() argument
258 if (cycle) in lock_graph_descend()
285 if (cycle) in bch2_check_for_deadlock()
296 if (cycle) in bch2_check_for_deadlock()
297 cycle->atomic++; in bch2_check_for_deadlock()
386 if (g.nr > 1 && cycle) in bch2_check_for_deadlock()
387 print_chain(cycle, &g); in bch2_check_for_deadlock()
391 if (cycle) in bch2_check_for_deadlock()
[all …]
/linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/
A Dhclge_ptp.c12 ptp->cycle.quo = readl(hdev->ptp->io_base + HCLGE_PTP_CYCLE_QUO_REG) & in hclge_ptp_get_cycle()
14 ptp->cycle.numer = readl(hdev->ptp->io_base + HCLGE_PTP_CYCLE_NUM_REG); in hclge_ptp_get_cycle()
15 ptp->cycle.den = readl(hdev->ptp->io_base + HCLGE_PTP_CYCLE_DEN_REG); in hclge_ptp_get_cycle()
17 if (ptp->cycle.den == 0) { in hclge_ptp_get_cycle()
28 struct hclge_ptp_cycle *cycle = &hdev->ptp->cycle; in hclge_ptp_adjfine() local
33 adj_base = (u64)cycle->quo * (u64)cycle->den + (u64)cycle->numer; in hclge_ptp_adjfine()
41 quo = div_u64_rem(adj_val, cycle->den, &numerator); in hclge_ptp_adjfine()
47 writel(cycle->den, hdev->ptp->io_base + HCLGE_PTP_CYCLE_DEN_REG); in hclge_ptp_adjfine()
/linux/Documentation/driver-api/thermal/
A Dcpu-idle-cooling.rst37 decrease. Acting on the idle state duration or the idle cycle
47 At a specific OPP, we can assume that injecting idle cycle on all CPUs
61 idle state for a specified time each control cycle, it provides
71 or decreased by modulating the duty cycle of the idle injection.
86 duty cycle 25%
90 the duty cycle percentage. When no mitigation is happening the cooling
91 device state is zero, meaning the duty cycle is 0%.
95 cycle (aka the cooling device state), the running duration can be
98 The governor will change the cooling device state thus the duty cycle
114 duty cycle 33%
[all …]
/linux/arch/arm/boot/dts/ti/omap/
A Domap3430-sdp.dts73 gpmc,rd-cycle-ns = <186>;
74 gpmc,wr-cycle-ns = <186>;
123 gpmc,rd-cycle-ns = <72>;
124 gpmc,wr-cycle-ns = <72>;
169 gpmc,rd-cycle-ns = <108>;
170 gpmc,wr-cycle-ns = <96>;

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