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Searched refs:dcc (Results 1 – 25 of 78) sorted by relevance

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/linux/Documentation/ABI/testing/
A Ddebugfs-driver-dcc1 What: /sys/kernel/debug/dcc/.../ready
5 This file is used to check the status of the dcc
7 A 'Y' here indicates dcc is ready.
9 What: /sys/kernel/debug/dcc/.../trigger
17 What: /sys/kernel/debug/dcc/.../config_reset
22 a dcc driver to the default configuration. When '1'
27 What: /sys/kernel/debug/dcc/.../[list-number]/config
34 can be one of following dcc instructions: read,
117 the dcc hardware. A file named "enable" is in the
122 On enabling the dcc, all the addresses specified
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/linux/Documentation/devicetree/bindings/soc/qcom/
A Dqcom,dcc.yaml4 $id: http://devicetree.org/schemas/soc/qcom/qcom,dcc.yaml#
21 - qcom,sm8150-dcc
22 - qcom,sc7280-dcc
23 - qcom,sc7180-dcc
24 - qcom,sdm845-dcc
25 - const: qcom,dcc
41 compatible = "qcom,sm8150-dcc", "qcom,dcc";
/linux/fs/f2fs/
A Dsegment.c1270 &(dcc->fstrim_list) : &(dcc->wait_list); in __submit_discard_cmd()
1592 dc = __lookup_discard_cmd_ret(&dcc->root, dcc->next_pos, in __issue_discard_cmd_orderly()
1626 dcc->next_pos = 0; in __issue_discard_cmd_orderly()
1762 &(dcc->fstrim_list) : &(dcc->wait_list); in __wait_discard_cmd_range()
1864 if (dcc && dcc->f2fs_issue_discard) { in f2fs_stop_discard_thread()
2308 if (!dcc) in create_discard_cmd_control()
2329 dcc->nr_discards = 0; in create_discard_cmd_control()
2337 dcc->next_pos = 0; in create_discard_cmd_control()
2346 kfree(dcc); in create_discard_cmd_control()
2357 if (!dcc) in destroy_discard_cmd_control()
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A Dsegment.h937 struct discard_cmd_control *dcc = SM_I(sbi)->dcc_info; in wake_up_discard_thread() local
944 mutex_lock(&dcc->cmd_lock); in wake_up_discard_thread()
946 if (i + 1 < dcc->discard_granularity) in wake_up_discard_thread()
948 if (!list_empty(&dcc->pend_list[i])) { in wake_up_discard_thread()
953 mutex_unlock(&dcc->cmd_lock); in wake_up_discard_thread()
957 dcc->discard_wake = true; in wake_up_discard_thread()
958 wake_up_interruptible_all(&dcc->discard_wait_queue); in wake_up_discard_thread()
/linux/Documentation/devicetree/bindings/serial/
A Darm,dcc.yaml4 $id: http://devicetree.org/schemas/serial/arm,dcc.yaml#
19 const: arm,dcc
29 compatible = "arm,dcc";
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn30/
A Ddcn30_hubp.c351 struct dc_plane_dcc_param *dcc) in hubp3_dcc_control_sienna_cichlid() argument
356 PRIMARY_SURFACE_DCC_EN, dcc->enable, in hubp3_dcc_control_sienna_cichlid()
357 PRIMARY_SURFACE_DCC_IND_BLK, dcc->dcc_ind_blk, in hubp3_dcc_control_sienna_cichlid()
358 PRIMARY_SURFACE_DCC_IND_BLK_C, dcc->dcc_ind_blk_c, in hubp3_dcc_control_sienna_cichlid()
359 SECONDARY_SURFACE_DCC_EN, dcc->enable, in hubp3_dcc_control_sienna_cichlid()
360 SECONDARY_SURFACE_DCC_IND_BLK, dcc->dcc_ind_blk, in hubp3_dcc_control_sienna_cichlid()
361 SECONDARY_SURFACE_DCC_IND_BLK_C, dcc->dcc_ind_blk_c); in hubp3_dcc_control_sienna_cichlid()
401 struct dc_plane_dcc_param *dcc, in hubp3_program_surface_config() argument
407 hubp3_dcc_control_sienna_cichlid(hubp, dcc); in hubp3_program_surface_config()
409 hubp2_program_size(hubp, format, plane_size, dcc); in hubp3_program_surface_config()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn201/
A Ddcn201_hubp.c48 struct dc_plane_dcc_param *dcc, in hubp201_program_surface_config() argument
52 hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); in hubp201_program_surface_config()
54 hubp1_program_size(hubp, format, plane_size, dcc); in hubp201_program_surface_config()
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm_plane.c264 const struct dc_plane_dcc_param *dcc, in amdgpu_dm_plane_validate_dcc() argument
275 if (!dcc->enable) in amdgpu_dm_plane_validate_dcc()
298 if (dcc->independent_64b_blks == 0 && in amdgpu_dm_plane_validate_dcc()
326 dcc->enable = 1; in amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers()
327 dcc->meta_pitch = afb->base.pitches[1]; in amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers()
377 dcc->enable = 1; in amdgpu_dm_plane_fill_gfx12_plane_attributes_from_modifiers()
381 dcc->dcc_ind_blk = hubp_ind_block_64b; in amdgpu_dm_plane_fill_gfx12_plane_attributes_from_modifiers()
840 struct dc_plane_dcc_param *dcc, in amdgpu_dm_plane_fill_plane_buffer_attributes() argument
850 memset(dcc, 0, sizeof(*dcc)); in amdgpu_dm_plane_fill_plane_buffer_attributes()
902 tiling_info, dcc, in amdgpu_dm_plane_fill_plane_buffer_attributes()
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A Damdgpu_dm_plane.h52 struct dc_plane_dcc_param *dcc,
/linux/drivers/bus/
A Dvexpress-config.c108 u32 *position, u32 *dcc) in vexpress_config_get_topo() argument
116 vexpress_config_find_prop(node, "arm,vexpress,dcc", dcc); in vexpress_config_get_topo()
257 u32 site, position, dcc; in vexpress_syscfg_regmap_init() local
261 &position, &dcc); in vexpress_syscfg_regmap_init()
301 func, site, position, dcc, in vexpress_syscfg_regmap_init()
304 func->template[i] = SYS_CFGCTRL_DCC(dcc); in vexpress_syscfg_regmap_init()
/linux/arch/arm64/boot/dts/xilinx/
A Dzynqmp-zcu1275-revA.dts22 serial1 = &dcc;
37 &dcc {
A Dzynqmp-zc1254-revA.dts22 serial1 = &dcc;
37 &dcc {
A Dzynqmp-zc1232-revA.dts21 serial1 = &dcc;
36 &dcc {
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn35/
A Ddcn35_hubp.c178 struct dc_plane_dcc_param *dcc, in hubp35_program_surface_config() argument
184 hubp3_dcc_control_sienna_cichlid(hubp, dcc); in hubp35_program_surface_config()
186 hubp2_program_size(hubp, format, plane_size, dcc); in hubp35_program_surface_config()
A Ddcn35_hubp.h71 struct dc_plane_dcc_param *dcc,
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/
A Ddml21_translation_helper.c613 surface->dcc.enable = false; in populate_dml21_dummy_surface_cfg()
614 surface->dcc.informative.dcc_rate_plane0 = 1.0; in populate_dml21_dummy_surface_cfg()
615 surface->dcc.informative.dcc_rate_plane1 = 1.0; in populate_dml21_dummy_surface_cfg()
616 surface->dcc.informative.fraction_of_zero_size_request_plane0 = 0; in populate_dml21_dummy_surface_cfg()
679 surface->dcc.enable = plane_state->dcc.enable; in populate_dml21_surface_config_from_plane_state()
680 surface->dcc.informative.dcc_rate_plane0 = 1.0; in populate_dml21_surface_config_from_plane_state()
681 surface->dcc.informative.dcc_rate_plane1 = 1.0; in populate_dml21_surface_config_from_plane_state()
682 …surface->dcc.informative.fraction_of_zero_size_request_plane0 = plane_state->dcc.independent_64b_b… in populate_dml21_surface_config_from_plane_state()
683 …surface->dcc.informative.fraction_of_zero_size_request_plane1 = plane_state->dcc.independent_64b_b… in populate_dml21_surface_config_from_plane_state()
684 surface->dcc.plane0.pitch = plane_state->dcc.meta_pitch; in populate_dml21_surface_config_from_plane_state()
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/linux/drivers/gpu/drm/i915/gt/
A Dintel_ggtt_fencing.c668 u32 dcc = intel_uncore_read(uncore, DCC); in detect_bit_6_swizzle() local
679 switch (dcc & DCC_ADDRESSING_MODE_MASK) { in detect_bit_6_swizzle()
686 if (dcc & DCC_CHANNEL_XOR_DISABLE) { in detect_bit_6_swizzle()
693 } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) { in detect_bit_6_swizzle()
712 if (dcc == 0xffffffff) { in detect_bit_6_swizzle()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn10/
A Ddcn10_hubp.c167 struct dc_plane_dcc_param *dcc) in hubp1_program_size() argument
180 meta_pitch = dcc->meta_pitch - 1; in hubp1_program_size()
182 meta_pitch_c = dcc->meta_pitch_c - 1; in hubp1_program_size()
185 meta_pitch = dcc->meta_pitch - 1; in hubp1_program_size()
190 if (!dcc->enable) { in hubp1_program_size()
541 struct dc_plane_dcc_param *dcc, in hubp1_program_surface_config() argument
545 hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); in hubp1_program_surface_config()
547 hubp1_program_size(hubp, format, plane_size, dcc); in hubp1_program_surface_config()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn401/
A Ddcn401_hubp.c512 struct dc_plane_dcc_param *dcc) in hubp401_dcc_control() argument
517 PRIMARY_SURFACE_DCC_EN, dcc->enable, in hubp401_dcc_control()
518 SECONDARY_SURFACE_DCC_EN, dcc->enable); in hubp401_dcc_control()
538 struct dc_plane_dcc_param *dcc) in hubp401_program_size() argument
574 struct dc_plane_dcc_param *dcc, in hubp401_program_surface_config() argument
580 hubp401_dcc_control(hubp, dcc); in hubp401_program_surface_config()
582 hubp401_program_size(hubp, format, plane_size, dcc); in hubp401_program_surface_config()
A Ddcn401_hubp.h289 struct dc_plane_dcc_param *dcc);
300 struct dc_plane_dcc_param *dcc);
308 struct dc_plane_dcc_param *dcc,
/linux/arch/arm/boot/dts/arm/
A Dvexpress-v2p-ca5s.dts144 dcc {
202 temp-dcc {
A Dvexpress-v2p-ca15-tc1.dts141 dcc {
217 temp-dcc {
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn20/
A Ddcn20_hubp.c332 struct dc_plane_dcc_param *dcc) in hubp2_program_size() argument
350 meta_pitch = dcc->meta_pitch - 1; in hubp2_program_size()
352 meta_pitch_c = dcc->meta_pitch_c - 1; in hubp2_program_size()
355 meta_pitch = dcc->meta_pitch - 1; in hubp2_program_size()
360 if (!dcc->enable) { in hubp2_program_size()
542 struct dc_plane_dcc_param *dcc, in hubp2_program_surface_config() argument
548 hubp2_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); in hubp2_program_surface_config()
550 hubp2_program_size(hubp, format, plane_size, dcc); in hubp2_program_surface_config()
/linux/drivers/s390/cio/
A Dqdio_main.c726 int dstat, int dcc) in qdio_establish_handle_irq() argument
734 if (dcc == 1) in qdio_establish_handle_irq()
754 int cstat, dstat, rc, dcc; in qdio_int_handler() local
774 dcc = scsw_cmd_is_valid_cc(&irb->scsw) ? irb->scsw.cmd.cc : 0; in qdio_int_handler()
779 rc = qdio_establish_handle_irq(irq_ptr, cstat, dstat, dcc); in qdio_int_handler()
793 else if (dcc == 1) in qdio_int_handler()
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dmem_input.h170 struct dc_plane_dcc_param *dcc,

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