| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| A D | dccg.h | 110 struct dccg *dccg,
115 struct dccg *dccg,
121 struct dccg *dccg,
126 struct dccg *dccg,
130 struct dccg *dccg,
135 struct dccg *dccg,
139 struct dccg *dccg,
144 struct dccg *dccg,
150 struct dccg *dccg,
167 struct dccg *dccg,
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn35/ |
| A D | dcn35_dccg.c | 163 struct dccg *dccg, in dccg35_set_symclk32_se_rcg() argument
202 struct dccg *dccg, in dccg35_set_symclk32_le_rcg() argument
229 struct dccg *dccg, in dccg35_set_physymclk_rcg() argument
266 struct dccg *dccg, in dccg35_set_symclk_fe_rcg() argument
313 struct dccg *dccg, in dccg35_set_symclk_be_rcg() argument
417 struct dccg *dccg, in dccg35_set_dpstreamclk_rcg() argument
516 struct dccg *dccg, in dccg35_set_symclk32_se_src_new() argument
568 struct dccg *dccg, in dccg35_set_symclk32_le_src_new() argument
616 struct dccg *dccg, in dccg35_set_dtbclk_p_src_new() argument
654 struct dccg *dccg, in dccg35_set_dpstreamclk_src_new() argument
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn401/ |
| A D | dcn401_dccg.c | 55 static void dcn401_set_dppclk_enable(struct dccg *dccg, in dcn401_set_dppclk_enable() argument
109 struct dccg *dccg) in dccg401_wait_for_dentist_change_done() argument
120 struct dccg *dccg, in dccg401_get_pixel_rate_div() argument
158 struct dccg *dccg, in dccg401_set_pixel_rate_div() argument
213 struct dccg *dccg, in dccg401_set_dtbclk_p_src() argument
268 struct dccg *dccg, in dccg401_set_physymclk() argument
382 struct dccg *dccg, in dccg401_enable_symclk32_le() argument
433 struct dccg *dccg, in dccg401_disable_symclk32_le() argument
578 struct dccg *dccg, in dccg401_set_dpstreamclk() argument
594 struct dccg *dccg, in dccg401_set_dp_dto() argument
[all …]
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| A D | dcn401_dccg.h | 193 void dccg401_init(struct dccg *dccg);
195 void dccg401_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);
198 struct dccg *dccg,
201 struct dccg *dccg401_create(
208 struct dccg *dccg,
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn31/ |
| A D | dcn31_dccg.c | 162 struct dccg *dccg, in dccg31_set_dpstreamclk() argument
174 struct dccg *dccg, in dccg31_enable_symclk32_se() argument
227 struct dccg *dccg, in dccg31_disable_symclk32_se() argument
277 struct dccg *dccg, in dccg31_enable_symclk32_le() argument
304 struct dccg *dccg, in dccg31_disable_symclk32_le() argument
328 struct dccg *dccg, in dccg31_set_symclk32_le_root_clock_gating() argument
443 struct dccg *dccg, in dccg31_set_physymclk() argument
545 struct dccg *dccg, in dccg31_set_dtbclk_dto() argument
611 struct dccg *dccg, in dccg31_set_audio_dtbclk_dto() argument
655 struct dccg *dccg, in dccg31_set_dispclk_change_mode() argument
[all …]
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| A D | dcn31_dccg.h | 171 struct dccg *dccg,
176 struct dccg *dccg,
180 struct dccg *dccg,
185 struct dccg *dccg,
189 struct dccg *dccg,
204 struct dccg *dccg,
209 struct dccg *dccg,
214 struct dccg *dccg,
224 struct dccg *dccg,
228 struct dccg *dccg,
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/ |
| A D | dcn20_dccg.c | 32 #define TO_DCN_DCCG(dccg)\ argument
45 dccg->ctx->logger
47 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg2_update_dpp_dto() argument
77 void dccg2_get_dccg_ref_freq(struct dccg *dccg, in dccg2_get_dccg_ref_freq() argument
99 void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg, in dccg2_set_fifo_errdet_ovr_en() argument
108 void dccg2_otg_add_pixel(struct dccg *dccg, in dccg2_otg_add_pixel() argument
120 void dccg2_otg_drop_pixel(struct dccg *dccg, in dccg2_otg_drop_pixel() argument
132 void dccg2_init(struct dccg *dccg) in dccg2_init() argument
152 struct dccg *base; in dccg2_create()
170 void dcn_dccg_destroy(struct dccg **dccg) in dcn_dccg_destroy() argument
[all …]
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| A D | dcn20_dccg.h | 432 struct dccg base;
438 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);
440 void dccg2_get_dccg_ref_freq(struct dccg *dccg,
444 void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg,
446 void dccg2_otg_add_pixel(struct dccg *dccg,
448 void dccg2_otg_drop_pixel(struct dccg *dccg,
452 void dccg2_init(struct dccg *dccg);
454 struct dccg *dccg2_create(
460 void dcn_dccg_destroy(struct dccg **dccg);
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn314/ |
| A D | dcn314_dccg.c | 46 dccg->ctx->logger
49 struct dccg *dccg) in dccg314_trigger_dio_fifo_resync() argument
59 struct dccg *dccg, in dccg314_get_pixel_rate_div() argument
101 struct dccg *dccg, in dccg314_set_pixel_rate_div() argument
149 struct dccg *dccg, in dccg314_set_dtbclk_p_src() argument
206 struct dccg *dccg, in dccg314_set_dtbclk_dto() argument
250 struct dccg *dccg, in dccg314_set_dpstreamclk() argument
288 static void dccg314_init(struct dccg *dccg) in dccg314_init() argument
315 struct dccg *dccg, in dccg314_set_valid_pixel_rate() argument
330 struct dccg *dccg, in dccg314_dpp_root_clock_control() argument
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn32/ |
| A D | dcn32_dccg.c | 43 dccg->ctx->logger
46 struct dccg *dccg) in dccg32_trigger_dio_fifo_resync() argument
59 struct dccg *dccg, in dccg32_get_pixel_rate_div() argument
101 struct dccg *dccg, in dccg32_set_pixel_rate_div() argument
149 struct dccg *dccg, in dccg32_set_dtbclk_p_src() argument
205 struct dccg *dccg, in dccg32_set_dtbclk_dto() argument
248 struct dccg *dccg, in dccg32_set_valid_pixel_rate() argument
263 static void dccg32_get_dccg_ref_freq(struct dccg *dccg, in dccg32_get_dccg_ref_freq() argument
276 struct dccg *dccg, in dccg32_set_dpstreamclk() argument
312 static void dccg32_otg_add_pixel(struct dccg *dccg, in dccg32_otg_add_pixel() argument
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn21/ |
| A D | dcn21_dccg.c | 31 #define TO_DCN_DCCG(dccg)\ argument
32 container_of(dccg, struct dcn_dccg, base)
44 dccg->ctx->logger
46 static void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg21_update_dpp_dto() argument
48 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg21_update_dpp_dto()
50 if (dccg->ref_dppclk) { in dccg21_update_dpp_dto()
51 int ref_dppclk = dccg->ref_dppclk; in dccg21_update_dpp_dto()
96 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg21_update_dpp_dto()
109 struct dccg *dccg21_create( in dccg21_create()
116 struct dccg *base; in dccg21_create()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/ |
| A D | Makefile | 31 AMD_DAL_DCCG_DCN20 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn20/,$(DCCG_DCN20))
39 AMD_DAL_DCCG_DCN201 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn201/,$(DCCG_DCN201))
47 AMD_DAL_DCCG_DCN21 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn21/,$(DCCG_DCN21))
54 AMD_DAL_DCCG_DCN30 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn30/,$(DCCG_DCN30))
61 AMD_DAL_DCCG_DCN301 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn301/,$(DCCG_DCN301))
69 AMD_DAL_DCCG_DCN31 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn31/,$(DCCG_DCN31))
77 AMD_DAL_DCCG_DCN314 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn314/,$(DCCG_DCN314))
85 AMD_DAL_DCCG_DCN32 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn32/,$(DCCG_DCN32))
93 AMD_DAL_DCCG_DCN35 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn35/,$(DCCG_DCN35))
100 AMD_DAL_DCCG_DCN401 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn401/,$(DCCG_DCN401))
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn201/ |
| A D | dcn201_dccg.c | 31 #define TO_DCN_DCCG(dccg)\ argument
32 container_of(dccg, struct dcn_dccg, base)
45 dccg->ctx->logger
47 static void dccg201_update_dpp_dto(struct dccg *dccg, int dpp_inst, in dccg201_update_dpp_dto() argument
62 struct dccg *dccg201_create( in dccg201_create()
69 struct dccg *base; in dccg201_create()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| A D | dcn20_clk_mgr.c | 155 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist() local
169 dccg, in dcn20_update_clocks_update_dentist()
172 dccg->funcs->otg_drop_pixel( in dcn20_update_clocks_update_dentist()
173 dccg, in dcn20_update_clocks_update_dentist()
176 dccg, in dcn20_update_clocks_update_dentist()
185 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist() local
199 dccg->funcs->set_fifo_errdet_ovr_en(dccg, true); in dcn20_update_clocks_update_dentist()
201 dccg->funcs->otg_add_pixel(dccg, in dcn20_update_clocks_update_dentist()
203 dccg->funcs->set_fifo_errdet_ovr_en(dccg, false); in dcn20_update_clocks_update_dentist()
532 struct dccg *dccg) in dcn20_clk_mgr_construct() argument
[all …]
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| A D | dcn20_clk_mgr.h | 29 void dcn2_update_clocks(struct clk_mgr *dccg,
44 struct dccg *dccg);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/ |
| A D | clk_mgr.c | 147 … clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg) in dc_clk_mgr_create() argument
233 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
238 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
260 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
264 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
268 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
275 dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
286 vg_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
299 dcn31_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
334 dcn32_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn30/ |
| A D | dcn30_dccg.c | 30 #define TO_DCN_DCCG(dccg)\ argument
31 container_of(dccg, struct dcn_dccg, base)
43 dccg->ctx->logger
55 struct dccg *dccg3_create( in dccg3_create()
62 struct dccg *base; in dccg3_create()
80 struct dccg *dccg30_create( in dccg30_create()
87 struct dccg *base; in dccg30_create()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn301/ |
| A D | dcn301_dccg.c | 30 #define TO_DCN_DCCG(dccg)\ argument
31 container_of(dccg, struct dcn_dccg, base)
43 dccg->ctx->logger
54 struct dccg *dccg301_create( in dccg301_create()
61 struct dccg *base; in dccg301_create()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| A D | dcn32_clk_mgr.c | 270 struct dccg *dccg = clk_mgr->dccg; in dcn32_update_clocks_update_dtb_dto() local
374 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn32_update_clocks_update_dentist() local
388 dccg, in dcn32_update_clocks_update_dentist()
392 dccg, in dcn32_update_clocks_update_dentist()
395 dccg, in dcn32_update_clocks_update_dentist()
427 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn32_update_clocks_update_dentist() local
441 dccg->funcs->set_fifo_errdet_ovr_en(dccg, true); in dcn32_update_clocks_update_dentist()
443 dccg->funcs->otg_add_pixel(dccg, in dcn32_update_clocks_update_dentist()
445 dccg->funcs->set_fifo_errdet_ovr_en(dccg, false); in dcn32_update_clocks_update_dentist()
1151 struct dccg *dccg) in dcn32_clk_mgr_construct() argument
[all …]
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| A D | dcn32_clk_mgr.h | 33 struct dccg *dccg);
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| /linux/drivers/gpu/drm/amd/display/dc/link/hwss/ |
| A D | link_hwss_hpo_dp.c | 118 if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating) in enable_hpo_dp_link_output()
119 link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating( in enable_hpo_dp_link_output()
120 link->dc->res_pool->dccg, in enable_hpo_dp_link_output()
142 if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating) in disable_hpo_dp_link_output()
143 link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating( in disable_hpo_dp_link_output()
144 link->dc->res_pool->dccg, in disable_hpo_dp_link_output()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn314/ |
| A D | dcn314_hwseq.c | 211 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc && in dcn314_dsc_pg_control()
213 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc( in dcn314_dsc_pg_control()
214 hws->ctx->dc->res_pool->dccg, dsc_inst); in dcn314_dsc_pg_control()
262 if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) in dcn314_dsc_pg_control()
263 hws->ctx->dc->res_pool->dccg->funcs->disable_dsc( in dcn314_dsc_pg_control()
264 hws->ctx->dc->res_pool->dccg, dsc_inst); in dcn314_dsc_pg_control()
381 hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg); in dcn314_resync_fifo_dccg_dio()
416 if (hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control) in dcn314_dpp_root_clock_control()
417 hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control( in dcn314_dpp_root_clock_control()
418 hws->ctx->dc->res_pool->dccg, dpp_inst, clock_on); in dcn314_dpp_root_clock_control()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| A D | dcn201_clk_mgr.h | 32 struct dccg *dccg);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| A D | dcn315_clk_mgr.h | 45 struct dccg *dccg);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| A D | dcn316_clk_mgr.h | 45 struct dccg *dccg);
|