| /linux/drivers/gpu/drm/sun4i/ |
| A D | sun4i_tcon_dclk.c | 74 struct sun4i_tcon *tcon = dclk->tcon; in sun4i_dclk_round_rate() 169 struct sun4i_dclk *dclk; in sun4i_dclk_create() local 179 dclk = devm_kzalloc(dev, sizeof(*dclk), GFP_KERNEL); in sun4i_dclk_create() 180 if (!dclk) in sun4i_dclk_create() 182 dclk->tcon = tcon; in sun4i_dclk_create() 190 dclk->regmap = tcon->regs; in sun4i_dclk_create() 191 dclk->hw.init = &init; in sun4i_dclk_create() 193 tcon->dclk = clk_register(dev, &dclk->hw); in sun4i_dclk_create() 194 if (IS_ERR(tcon->dclk)) in sun4i_dclk_create() 195 return PTR_ERR(tcon->dclk); in sun4i_dclk_create() [all …]
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| /linux/drivers/clk/hisilicon/ |
| A D | clkdivider-hi6220.c | 51 val = readl_relaxed(dclk->reg) >> dclk->shift; in hi6220_clkdiv_recalc_rate() 52 val &= div_mask(dclk->width); in hi6220_clkdiv_recalc_rate() 76 dclk->width, CLK_DIVIDER_ROUND_CLOSEST); in hi6220_clkdiv_set_rate() 78 if (dclk->lock) in hi6220_clkdiv_set_rate() 79 spin_lock_irqsave(dclk->lock, flags); in hi6220_clkdiv_set_rate() 81 data = readl_relaxed(dclk->reg); in hi6220_clkdiv_set_rate() 82 data &= ~(div_mask(dclk->width) << dclk->shift); in hi6220_clkdiv_set_rate() 83 data |= value << dclk->shift; in hi6220_clkdiv_set_rate() 84 data |= dclk->mask; in hi6220_clkdiv_set_rate() 86 writel_relaxed(data, dclk->reg); in hi6220_clkdiv_set_rate() [all …]
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| /linux/drivers/clk/nuvoton/ |
| A D | clk-ma35d1-divider.c | 35 val = readl_relaxed(dclk->reg) >> dclk->shift; in ma35d1_clkdiv_recalc_rate() 36 val &= clk_div_mask(dclk->width); in ma35d1_clkdiv_recalc_rate() 47 dclk->width, CLK_DIVIDER_ROUND_CLOSEST); in ma35d1_clkdiv_round_rate() 58 dclk->width, CLK_DIVIDER_ROUND_CLOSEST); in ma35d1_clkdiv_set_rate() 60 spin_lock_irqsave(dclk->lock, flags); in ma35d1_clkdiv_set_rate() 62 data = readl_relaxed(dclk->reg); in ma35d1_clkdiv_set_rate() 63 data &= ~(clk_div_mask(dclk->width) << dclk->shift); in ma35d1_clkdiv_set_rate() 64 data |= (value - 1) << dclk->shift; in ma35d1_clkdiv_set_rate() 65 data |= dclk->mask; in ma35d1_clkdiv_set_rate() 66 writel_relaxed(data, dclk->reg); in ma35d1_clkdiv_set_rate() [all …]
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| /linux/drivers/siox/ |
| A D | siox-bus-gpio.c | 20 struct gpio_desc *dclk; member 38 gpiod_set_value_cansleep(ddata->dclk, 0); in siox_gpio_pushpull() 60 gpiod_set_value_cansleep(ddata->dclk, 1); in siox_gpio_pushpull() 62 gpiod_set_value_cansleep(ddata->dclk, 0); in siox_gpio_pushpull() 112 ddata->dclk = devm_gpiod_get(dev, "dclk", GPIOD_OUT_LOW); in siox_gpio_probe() 113 if (IS_ERR(ddata->dclk)) in siox_gpio_probe() 114 return dev_err_probe(dev, PTR_ERR(ddata->dclk), in siox_gpio_probe()
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| /linux/Documentation/devicetree/bindings/display/ |
| A D | solomon,ssd1307fb.yaml | 87 solomon,dclk-div: 94 solomon,dclk-frq: 138 solomon,dclk-div: 140 solomon,dclk-frq: 156 solomon,dclk-div: 158 solomon,dclk-frq: 174 solomon,dclk-div: 176 solomon,dclk-frq: 192 solomon,dclk-div: 194 solomon,dclk-frq: [all …]
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| /linux/drivers/clk/ |
| A D | clk-lmk04832.c | 267 struct lmk_dclk *dclk; member 1014 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_is_enabled() 1029 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_prepare() 1039 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_unprepare() 1050 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_recalc_rate() 1076 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_round_rate() 1098 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_set_rate() 1311 lmk->dclk[dclk_num].id = num; in lmk04832_register_clkout() 1312 lmk->dclk[dclk_num].lmk = lmk; in lmk04832_register_clkout() 1313 lmk->dclk[dclk_num].hw.init = &init; in lmk04832_register_clkout() [all …]
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| /linux/drivers/video/fbdev/riva/ |
| A D | nv_driver.c | 276 unsigned long dclk = 0; in riva_get_maxdclk() local 286 dclk = 800000; in riva_get_maxdclk() 288 dclk = 1000000; in riva_get_maxdclk() 294 dclk = 1000000; in riva_get_maxdclk() 303 dclk = 800000; in riva_get_maxdclk() 306 dclk = 1000000; in riva_get_maxdclk() 311 return dclk; in riva_get_maxdclk()
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| /linux/drivers/gpu/drm/i915/display/ |
| A D | intel_bw.c | 22 u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd; member 59 sp->dclk *= 2; in dg1_mchbar_read_qgv_point_info() 61 if (sp->dclk == 0) in dg1_mchbar_read_qgv_point_info() 82 u16 dclk; in icl_pcode_read_qgv_point_info() local 91 dclk = val & 0xffff; in icl_pcode_read_qgv_point_info() 92 sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(dev_priv) >= 12 ? 500 : 0), in icl_pcode_read_qgv_point_info() 183 u16 dclk; in mtl_read_qgv_point_info() local 190 sp->dclk = DIV_ROUND_CLOSEST(16667 * dclk, 1000); in mtl_read_qgv_point_info() 339 u16 dclk = 0; in icl_sagv_max_dclk() local 343 dclk = max(dclk, qi->points[i].dclk); in icl_sagv_max_dclk() [all …]
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| /linux/sound/soc/meson/ |
| A D | axg-pdm.c | 94 struct clk *dclk; member 188 clk_get_rate(priv->dclk) * 2); in axg_pdm_set_sample_pointer() 253 ret = clk_set_rate(priv->dclk, rate * os); in axg_pdm_hw_params() 276 ret = clk_prepare_enable(priv->dclk); in axg_pdm_startup() 294 clk_disable_unprepare(priv->dclk); in axg_pdm_shutdown() 618 priv->dclk = devm_clk_get(dev, "dclk"); in axg_pdm_probe() 619 if (IS_ERR(priv->dclk)) in axg_pdm_probe() 620 return dev_err_probe(dev, PTR_ERR(priv->dclk), "failed to get dclk\n"); in axg_pdm_probe()
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| /linux/Documentation/devicetree/bindings/siox/ |
| A D | eckelmann,siox-gpio.txt | 5 - din-gpios, dout-gpios, dclk-gpios, dld-gpios: references gpios for the 17 dclk-gpios = <&gpio6 9 0>;
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| /linux/drivers/gpu/drm/renesas/rz-du/ |
| A D | rzg2l_du_crtc.c | 72 clk_prepare_enable(rcrtc->rzg2l_clocks.dclk); in rzg2l_du_crtc_set_display_timing() 73 clk_set_rate(rcrtc->rzg2l_clocks.dclk, mode_clock); in rzg2l_du_crtc_set_display_timing() 210 clk_disable_unprepare(rcrtc->rzg2l_clocks.dclk); in rzg2l_du_crtc_put() 407 rcrtc->rzg2l_clocks.dclk = devm_clk_get(rcdu->dev, "vclk"); in rzg2l_du_crtc_create() 408 if (IS_ERR(rcrtc->rzg2l_clocks.dclk)) { in rzg2l_du_crtc_create() 410 return PTR_ERR(rcrtc->rzg2l_clocks.dclk); in rzg2l_du_crtc_create()
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| A D | rzg2l_du_crtc.h | 61 struct clk *dclk; member
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| /linux/drivers/video/fbdev/core/ |
| A D | fbmon.c | 1017 u32 dclk; member 1109 dclk /= 1000; in fb_get_hblank_by_dclk() 1112 h_period += (M_VAL * xres * 2 * 1000)/(5 * dclk); in fb_get_hblank_by_dclk() 1156 timings->dclk = timings->htotal * timings->hfreq; in fb_timings_vfreq() 1167 timings->dclk = timings->htotal * timings->hfreq; in fb_timings_hfreq() 1175 timings->hfreq = timings->dclk/timings->htotal; in fb_timings_dclk() 1267 if (timings->dclk > dclkmax) { in fb_get_mode() 1268 timings->dclk = dclkmax; in fb_get_mode() 1281 timings->dclk = PICOS2KHZ(val) * 1000; in fb_get_mode() 1292 timings->dclk < dclkmin || timings->dclk > dclkmax))) { in fb_get_mode() [all …]
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| /linux/drivers/gpu/drm/radeon/ |
| A D | rs780_dpm.c | 571 (new_ps->dclk == old_ps->dclk)) in rs780_set_uvd_clock_before_set_eng_clock() 577 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_before_set_eng_clock() 588 (new_ps->dclk == old_ps->dclk)) in rs780_set_uvd_clock_after_set_eng_clock() 594 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_after_set_eng_clock() 728 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in rs780_parse_pplib_non_clock_info() 731 rps->dclk = 0; in rs780_parse_pplib_non_clock_info() 735 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rs780_parse_pplib_non_clock_info() 737 rps->dclk = RS780_DEFAULT_DCLK_FREQ; in rs780_parse_pplib_non_clock_info() 945 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_print_power_state() 994 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_debugfs_print_current_performance_level()
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| A D | trinity_dpm.c | 850 if ((rps->vclk == 0) && (rps->dclk == 0)) in trinity_uvd_clocks_zero() 863 (rps1->dclk == rps2->dclk) && in trinity_uvd_clocks_equal() 895 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks() 906 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks() 1411 (rps->dclk == pi->sys_info.uvd_clock_table_entries[i].dclk)) in trinity_get_uvd_clock_index() 1645 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in trinity_parse_pplib_non_clock_info() 1648 rps->dclk = 0; in trinity_parse_pplib_non_clock_info() 1890 pi->sys_info.uvd_clock_table_entries[i].dclk = in trinity_parse_sys_info_table() 1973 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_print_power_state() 1998 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_debugfs_print_current_performance_level()
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| A D | sumo_dpm.c | 822 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in sumo_setup_uvd_clocks() 839 (new_rps->dclk == old_rps->dclk)) in sumo_set_uvd_clock_before_set_eng_clock() 857 (new_rps->dclk == old_rps->dclk)) in sumo_set_uvd_clock_after_set_eng_clock() 1413 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in sumo_parse_pplib_non_clock_info() 1416 rps->dclk = 0; in sumo_parse_pplib_non_clock_info() 1804 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_print_power_state() 1827 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level() 1835 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
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| A D | trinity_dpm.h | 69 u32 dclk; member
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| /linux/Documentation/devicetree/bindings/sound/ |
| A D | amlogic,axg-pdm.yaml | 37 - const: dclk 81 clock-names = "pclk", "dclk", "sysclk";
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| /linux/arch/arm/boot/dts/ti/omap/ |
| A D | dra7xx-clocks.dtsi | 361 mpu_dclk_div: clock-mpu-dclk-div { 470 iva_dclk: clock-iva-dclk { 615 video2_dclk_div: clock-video2-dclk-div { 624 video1_dclk_div: clock-video1-dclk-div { 633 hdmi_dclk_div: clock-hdmi-dclk-div { 706 eve_dclk_div: clock-eve-dclk-div { 1113 gpu_dclk: clock-gpu-dclk@1a0 { 1172 sata_dclk_div: clock-sata-dclk-div@1c0 { 1182 pcie2_dclk_div: clock-pcie2-dclk-div@1b8 { 1192 pcie_dclk_div: clock-pcie-dclk-div@1b4 { [all …]
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| /linux/Documentation/devicetree/bindings/display/rockchip/ |
| A D | rockchip-vop.yaml | 71 - const: dclk 118 reset-names = "axi", "ahb", "dclk";
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| A D | rockchip-vop2.yaml | 71 Phandle to GRF regs used for control the polarity of dclk/hsync/vsync of DPI, 77 Phandle to VO GRF regs used for control the polarity of dclk/hsync/vsync of hdmi
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| /linux/drivers/gpu/drm/rockchip/ |
| A D | rockchip_drm_vop.c | 177 struct clk *dclk; member 634 ret = clk_enable(vop->dclk); in vop_enable() 702 clk_disable(vop->dclk); in vop_enable() 775 clk_disable(vop->dclk); in vop_crtc_atomic_disable() 1245 rate = clk_round_rate(vop->dclk, in vop_crtc_mode_fixup() 2017 vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); in vop_initial() 2018 if (IS_ERR(vop->dclk)) { in vop_initial() 2020 return PTR_ERR(vop->dclk); in vop_initial() 2029 ret = clk_prepare(vop->dclk); in vop_initial() 2109 clk_unprepare(vop->dclk); in vop_initial() [all …]
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| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| A D | hwmgr_ppt.h | 59 uint32_t dclk; /* UVD D-clock */ member
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| /linux/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| A D | power_state.h | 185 unsigned long dclk; member
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| /linux/include/linux/mfd/ |
| A D | si476x-platform.h | 121 enum si476x_dclk_config dclk; member
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