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Searched refs:dcn_reg_offsets (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dmub/src/
A Ddmub_dcn351.c11 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
A Ddmub_dcn32.c35 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
A Ddmub_dcn35.c35 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn35/
A Dirq_service_dcn35.c193 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn351/
A Dirq_service_dcn351.c172 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
/linux/drivers/gpu/drm/amd/display/dc/
A Ddc_types.h799 uint32_t *dcn_reg_offsets; member
A Ddc.h1120 uint32_t *dcn_reg_offsets; member
1448 uint32_t *dcn_reg_offsets; member
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/
A Ddcn321_resource.c113 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
198 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
1081 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS, in read_dce_straps()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/
A Ddcn401_resource.c98 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
189 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
1073 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS, in read_dce_straps()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
A Ddcn32_resource.c112 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
198 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
1098 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS, in read_dce_straps()
/linux/drivers/gpu/drm/amd/display/dc/core/
A Ddc.c933 dc_ctx->dcn_reg_offsets = init_params->dcn_reg_offsets; in dc_construct_ctx()
1392 dc->dcn_reg_offsets = init_params->dcn_reg_offsets; in dc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/
A Ddcn35_resource.c127 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/
A Ddcn351_resource.c107 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm.c1921 init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0]; in amdgpu_dm_init()

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