Searched refs:ddr50 (Results 1 – 25 of 45) sorted by relevance
12
| /linux/Documentation/devicetree/bindings/mmc/ |
| A D | sdhci-omap.txt | 19 "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104",
|
| A D | sdhci-st.txt | 57 - sd-uhs-ddr50: To enable the DDR50 in the mmcss.
109 sd-uhs-ddr50;
|
| A D | brcm,sdhci-brcmstb.yaml | 93 sd-uhs-ddr50;
|
| A D | sdhci-am654.yaml | 103 ti,otap-del-sel-ddr50:
161 ti,itap-del-sel-ddr50:
|
| A D | cdns,sdhci.yaml | 69 cdns,phy-input-delay-sd-uhs-ddr50:
|
| A D | samsung,exynos-dw-mshc.yaml | 166 sd-uhs-ddr50;
|
| A D | mmc-controller.yaml | 160 sd-uhs-ddr50:
348 "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":
|
| /linux/arch/arm/boot/dts/st/ |
| A D | stih410-b2120.dts | 41 sd-uhs-ddr50;
|
| A D | stih418-b2199.dts | 94 sd-uhs-ddr50;
|
| A D | stm32mp157c-ed1.dts | 374 sd-uhs-ddr50;
|
| /linux/arch/arm64/boot/dts/broadcom/ |
| A D | bcm2712-rpi-5-b.dts | 62 sd-uhs-ddr50;
|
| /linux/arch/arm/boot/dts/ti/omap/ |
| A D | dra72-evm.dts | 94 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
|
| A D | dra72-evm-revc.dts | 124 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
|
| A D | dra7-evm.dts | 389 …pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50"…
|
| A D | dra72x-mmc-iodelay.dtsi | 90 mmc1_pins_ddr50_rev10: mmc1-ddr50-rev10-pins {
101 mmc1_pins_ddr50_rev20: mmc1-ddr50-rev20-pins {
|
| A D | dra71-evm.dts | 203 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
|
| /linux/arch/arm64/boot/dts/amd/ |
| A D | elba.dtsi | 181 cdns,phy-input-delay-sd-uhs-ddr50 = <0x16>;
|
| /linux/arch/arm64/boot/dts/amlogic/ |
| A D | meson-gxl-s905x-libretech-cc-v2.dts | 254 sd-uhs-ddr50;
|
| A D | meson-gx-libretech-pc.dtsi | 385 sd-uhs-ddr50;
|
| A D | meson-gxbb-nanopi-k2.dts | 352 sd-uhs-ddr50;
|
| /linux/arch/arm64/boot/dts/freescale/ |
| A D | imx8mm-phg.dts | 243 sd-uhs-ddr50;
|
| /linux/arch/arm64/boot/dts/xilinx/ |
| A D | zynqmp-sck-kv-g-revB.dtso | 157 clk-phase-uhs-ddr50 = <126>, <48>;
|
| /linux/include/linux/ |
| A D | rtsx_pci.h | 1302 #define SET_CLOCK_PHASE(sdr104, sdr50, ddr50) \ argument
1303 (((ddr50) << 16) | ((sdr50) << 8) | (sdr104))
|
| /linux/arch/arm/boot/dts/rockchip/ |
| A D | rk3288-firefly-reload.dts | 265 sd-uhs-ddr50;
|
| /linux/arch/arm/boot/dts/nxp/imx/ |
| A D | imx6qdl-skov-cpu.dtsi | 336 sd-uhs-ddr50;
|
Completed in 40 milliseconds
12