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Searched refs:dev_priv (Results 1 – 25 of 255) sorted by relevance

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/linux/drivers/gpu/drm/i915/soc/
A Dintel_pch.c17 drm_WARN_ON(&dev_priv->drm, GRAPHICS_VER(dev_priv) != 5); in intel_pch_type()
22 GRAPHICS_VER(dev_priv) != 6 && !IS_IVYBRIDGE(dev_priv)); in intel_pch_type()
27 GRAPHICS_VER(dev_priv) != 6 && !IS_IVYBRIDGE(dev_priv)); in intel_pch_type()
33 !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); in intel_pch_type()
40 !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); in intel_pch_type()
47 !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); in intel_pch_type()
55 !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); in intel_pch_type()
63 !IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv)); in intel_pch_type()
114 drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv)); in intel_pch_type()
125 drm_WARN_ON(&dev_priv->drm, !IS_TIGERLAKE(dev_priv) && in intel_pch_type()
[all …]
A Dintel_pch.h66 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) argument
67 #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id) argument
68 #define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG2) argument
69 #define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP) argument
70 #define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG1) argument
71 #define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP) argument
72 #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP) argument
73 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP) argument
74 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT) argument
75 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT) argument
[all …]
/linux/drivers/gpu/drm/xe/compat-i915-headers/
A Di915_drv.h26 #define IS_I830(dev_priv) (dev_priv && 0) argument
27 #define IS_I845G(dev_priv) (dev_priv && 0) argument
28 #define IS_I85X(dev_priv) (dev_priv && 0) argument
29 #define IS_I865G(dev_priv) (dev_priv && 0) argument
30 #define IS_I915G(dev_priv) (dev_priv && 0) argument
32 #define IS_I945G(dev_priv) (dev_priv && 0) argument
34 #define IS_I965G(dev_priv) (dev_priv && 0) argument
36 #define IS_G45(dev_priv) (dev_priv && 0) argument
37 #define IS_GM45(dev_priv) (dev_priv && 0) argument
38 #define IS_G4X(dev_priv) (dev_priv && 0) argument
[all …]
/linux/drivers/gpu/drm/i915/
A Di915_suspend.c41 if (GRAPHICS_VER(dev_priv) == 2 && IS_MOBILE(dev_priv)) { in intel_save_swf()
43 dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, in intel_save_swf()
45 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, in intel_save_swf()
75 intel_de_write(dev_priv, SWF0(dev_priv, i), in intel_restore_swf()
77 intel_de_write(dev_priv, SWF1(dev_priv, i), in intel_restore_swf()
81 intel_de_write(dev_priv, SWF3(dev_priv, i), in intel_restore_swf()
85 intel_de_write(dev_priv, SWF1(dev_priv, i), in intel_restore_swf()
89 intel_de_write(dev_priv, SWF0(dev_priv, i), in intel_restore_swf()
91 intel_de_write(dev_priv, SWF1(dev_priv, i), in intel_restore_swf()
95 intel_de_write(dev_priv, SWF3(dev_priv, i), in intel_restore_swf()
[all …]
A Di915_irq.c192 if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice)) in ivb_parity_work()
229 drm_dbg(&dev_priv->drm, in ivb_parity_work()
242 drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice); in ivb_parity_work()
670 if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv)) in ibx_irq_reset()
693 ibx_irq_reset(dev_priv); in ilk_irq_reset()
887 dev_priv->irq_mask = in i8xx_irq_postinstall()
1060 dev_priv->irq_mask = in i915_irq_postinstall()
1187 dev_priv->irq_mask = in i965_irq_postinstall()
1202 if (IS_G4X(dev_priv)) in i965_irq_postinstall()
1293 if (HAS_GT_UC(dev_priv) && GRAPHICS_VER(dev_priv) < 11) in intel_irq_init()
[all …]
A Di915_driver.c179 pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6; in intel_detect_preproduction_hw()
180 pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA; in intel_detect_preproduction_hw()
181 pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; in intel_detect_preproduction_hw()
182 pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3; in intel_detect_preproduction_hw()
183 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7; in intel_detect_preproduction_hw()
184 pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; in intel_detect_preproduction_hw()
185 pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1; in intel_detect_preproduction_hw()
186 pre |= IS_DG2_G10(dev_priv) && INTEL_REVID(dev_priv) < 0x8; in intel_detect_preproduction_hw()
187 pre |= IS_DG2_G11(dev_priv) && INTEL_REVID(dev_priv) < 0x5; in intel_detect_preproduction_hw()
188 pre |= IS_DG2_G12(dev_priv) && INTEL_REVID(dev_priv) < 0x1; in intel_detect_preproduction_hw()
[all …]
/linux/drivers/gpu/drm/i915/display/
A Dintel_display_irq.c54 !drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) { in ilk_update_display_irq()
56 intel_uncore_write(&dev_priv->uncore, DEIMR, dev_priv->irq_mask); in ilk_update_display_irq()
87 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) in bdw_update_port_irq()
119 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) in bdw_update_pipe_irq()
237 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)); in i915_enable_pipestat()
260 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)); in i915_disable_pipestat()
390 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) in i9xx_pipe_crc_irq_handler()
1110 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in gen8_de_irq_handler()
1488 drm_WARN_ON(&dev_priv->drm, dev_priv->irq_mask != ~0u); in vlv_display_irq_postinstall()
1741 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in gen8_de_irq_postinstall()
[all …]
A Dintel_display_power_well.c413 drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv)); in icl_combo_phy_aux_power_well_enable()
440 drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv)); in icl_combo_phy_aux_power_well_disable()
597 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) && in hsw_power_well_enabled()
617 drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv), in assert_can_enable_dc9()
697 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in gen9_dc_mask()
822 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) in gen9_enable_dc5()
853 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) in skl_enable_dc6()
993 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in gen9_disable_dc_states()
1173 intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv), in vlv_init_display_clock_gating()
1204 u32 val = intel_de_read(dev_priv, DPLL(dev_priv, pipe)); in vlv_display_power_well_init()
[all …]
A Dintel_fifo_underrun.c125 intel_de_write(dev_priv, reg, in i9xx_set_fifo_underrun_reporting()
184 drm_err(&dev_priv->drm, in ivb_set_fifo_underrun_reporting()
212 intel_de_write(dev_priv, in bdw_set_fifo_underrun_reporting()
275 drm_err(&dev_priv->drm, in cpt_set_fifo_underrun_reporting()
294 if (HAS_GMCH(dev_priv)) in __intel_set_cpu_fifo_underrun_reporting()
296 else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv)) in __intel_set_cpu_fifo_underrun_reporting()
373 if (HAS_PCH_IBX(dev_priv)) in intel_set_pch_fifo_underrun_reporting()
406 if (HAS_GMCH(dev_priv) && in intel_cpu_fifo_underrun_irq_handler()
425 intel_de_write(dev_priv, ICL_PIPESTATUS(dev_priv, pipe), in intel_cpu_fifo_underrun_irq_handler()
485 if (HAS_GMCH(dev_priv)) in intel_check_cpu_fifo_underruns()
[all …]
A Dintel_pch_refclk.c33 lpt_fdi_reset_mphy(dev_priv); in lpt_fdi_program_mphy()
111 mutex_lock(&dev_priv->sb_lock); in lpt_disable_iclkip()
183 lpt_disable_iclkip(dev_priv); in lpt_program_iclkip()
194 drm_dbg_kms(&dev_priv->drm, in lpt_program_iclkip()
198 mutex_lock(&dev_priv->sb_lock); in lpt_program_iclkip()
278 if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) && in lpt_enable_clkout_dp()
407 if (IS_BROADWELL(dev_priv) && in spll_uses_pch_ssc()
426 if ((IS_BROADWELL(dev_priv) || IS_HASWELL_ULT(dev_priv)) && in wrpll_uses_pch_ssc()
522 if (HAS_PCH_IBX(dev_priv)) { in ilk_init_pch_refclk()
546 drm_dbg_kms(&dev_priv->drm, in ilk_init_pch_refclk()
[all …]
A Dintel_pch_display.c51 I915_STATE_WARN(dev_priv, in assert_pch_dp_disabled()
70 I915_STATE_WARN(dev_priv, in assert_pch_hdmi_disabled()
85 I915_STATE_WARN(dev_priv, in assert_pch_ports_disabled()
90 I915_STATE_WARN(dev_priv, in assert_pch_ports_disabled()
227 intel_de_read(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder))); in ilk_pch_transcoder_set_timings()
229 intel_de_read(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder))); in ilk_pch_transcoder_set_timings()
231 intel_de_read(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder))); in ilk_pch_transcoder_set_timings()
234 intel_de_read(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder))); in ilk_pch_transcoder_set_timings()
236 intel_de_read(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder))); in ilk_pch_transcoder_set_timings()
238 intel_de_read(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder))); in ilk_pch_transcoder_set_timings()
[all …]
A Dintel_fdi.c31 if (HAS_DDI(dev_priv)) { in assert_fdi_tx()
194 drm_dbg_kms(&dev_priv->drm, in ilk_check_fdi_lanes()
198 drm_dbg_kms(&dev_priv->drm, in ilk_check_fdi_lanes()
204 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { in ilk_check_fdi_lanes()
424 drm_WARN_ON(&dev_priv->drm, in cpt_set_fdi_bc_bifurcation()
427 drm_WARN_ON(&dev_priv->drm, in cpt_set_fdi_bc_bifurcation()
501 if (IS_IVYBRIDGE(dev_priv)) in intel_fdi_normal_train()
520 intel_de_read(dev_priv, PIPE_DATA_M1(dev_priv, pipe)) & TU_SIZE_MASK); in ilk_fdi_link_train()
622 intel_de_read(dev_priv, PIPE_DATA_M1(dev_priv, pipe)) & TU_SIZE_MASK); in gen6_fdi_link_train()
760 intel_de_read(dev_priv, PIPE_DATA_M1(dev_priv, pipe)) & TU_SIZE_MASK); in ivb_manual_fdi_link_train()
[all …]
A Dintel_cdclk.c127 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); in intel_cdclk_get_cdclk()
597 if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) { in vlv_program_pfi_credits()
2083 if (DISPLAY_VER(dev_priv) >= 14 || IS_DG2(dev_priv)) in bxt_set_cdclk()
2125 else if (DISPLAY_VER(dev_priv) >= 11 && !IS_DG2(dev_priv)) in bxt_set_cdclk()
2374 if (DISPLAY_VER(dev_priv) < 10 && !IS_BROXTON(dev_priv)) in intel_cdclk_can_cd2x_update()
2699 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) in intel_pixel_rate_to_cdclk()
2812 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_crtc_compute_min_cdclk()
3383 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) in intel_compute_max_dotclk()
3403 if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { in intel_update_max_cdclk()
3488 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_update_cdclk()
[all …]
A Dintel_display_power.c936 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in get_allowed_dc_mask()
948 mask = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) || in get_allowed_dc_mask()
1005 get_allowed_dc_mask(dev_priv, dev_priv->display.params.enable_dc); in intel_power_domains_init()
1133 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) in icl_mbus_init()
1186 I915_STATE_WARN(dev_priv, intel_de_read(dev_priv, HSW_PWR_WELL_CTL2), in assert_can_disable_lcpll()
1198 intel_de_read(dev_priv, PP_STATUS(dev_priv, 0)) & PP_ON, in assert_can_disable_lcpll()
1223 I915_STATE_WARN(dev_priv, intel_irqs_enabled(dev_priv), in assert_can_disable_lcpll()
1425 intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); in skl_display_core_init()
1588 if (IS_DGFX(dev_priv) && !IS_DG1(dev_priv)) in tgl_bw_buddy_init()
1638 intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); in icl_display_core_init()
[all …]
A Dintel_combo_phy.c98 drm_dbg(&dev_priv->drm, in check_phy_reg()
152 if (!has_phy_misc(dev_priv, phy)) in icl_combo_phy_enabled()
209 else if (IS_ALDERLAKE_S(dev_priv)) in phy_is_master()
211 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) in phy_is_master()
226 if (DISPLAY_VER(dev_priv) >= 12) { in icl_combo_phy_verify_state()
243 if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { in icl_combo_phy_verify_state()
321 drm_dbg(&dev_priv->drm, in icl_combo_phys_init()
337 if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) && in icl_combo_phys_init()
381 if (IS_TIGERLAKE(dev_priv) || IS_DG1(dev_priv)) { in icl_combo_phys_uninit()
387 drm_dbg_kms(&dev_priv->drm, in icl_combo_phys_uninit()
[all …]
A Dintel_lpe_audio.c80 #define HAS_LPE_AUDIO(dev_priv) ((dev_priv)->display.audio.lpe.platdev != NULL) argument
133 drm_err(&dev_priv->drm, in lpe_audio_platdev_create()
174 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)); in lpe_audio_irq_init()
187 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in lpe_audio_detect()
197 drm_info(&dev_priv->drm, in lpe_audio_detect()
217 drm_dbg(&dev_priv->drm, "irq = %d\n", dev_priv->display.audio.lpe.irq); in lpe_audio_setup()
222 drm_err(&dev_priv->drm, in lpe_audio_setup()
228 dev_priv->display.audio.lpe.platdev = lpe_audio_platdev_create(dev_priv); in lpe_audio_setup()
232 drm_err(&dev_priv->drm, in lpe_audio_setup()
264 if (!HAS_LPE_AUDIO(dev_priv)) in intel_lpe_audio_irq_handler()
[all …]
A Dintel_hotplug.c167 drm_dbg_kms(&dev_priv->drm, in intel_hpd_irq_storm_detect()
171 drm_dbg_kms(&dev_priv->drm, in intel_hpd_irq_storm_detect()
241 drm_info(&dev_priv->drm, in intel_hpd_irq_storm_switch_to_polling()
284 drm_dbg(&dev_priv->drm, in intel_hpd_irq_storm_reenable_work()
569 drm_dbg(&dev_priv->drm, in intel_hpd_irq_handler()
598 drm_WARN_ONCE(&dev_priv->drm, !HAS_GMCH(dev_priv), in intel_hpd_irq_handler()
641 queue_work(dev_priv->display.hotplug.dp_wq, &dev_priv->display.hotplug.dig_port_work); in intel_hpd_irq_handler()
667 if (!HAS_DISPLAY(dev_priv)) in intel_hpd_init()
749 drm_WARN_ON(&dev_priv->drm, in i915_hpd_poll_init_work()
852 if (!HAS_DISPLAY(dev_priv)) in intel_hpd_poll_disable()
[all …]
A Dintel_crt.c196 intel_de_write(dev_priv, BCLRPAT(dev_priv, crtc->pipe), 0); in intel_crt_set_dpms()
606 if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN(dev_priv), in intel_crt_detect_hotplug()
612 stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT(dev_priv)); in intel_crt_detect_hotplug()
617 intel_de_write(dev_priv, PORT_HOTPLUG_STAT(dev_priv), in intel_crt_detect_hotplug()
725 intel_de_write(dev_priv, BCLRPAT(dev_priv, cpu_transcoder), 0x500050); in intel_crt_load_detect()
731 intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), in intel_crt_load_detect()
743 intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), in intel_crt_load_detect()
774 while (intel_de_read(dev_priv, PIPEDSL(dev_priv, pipe)) >= vactive) in intel_crt_load_detect()
789 } while ((intel_de_read(dev_priv, PIPEDSL(dev_priv, pipe)) == dsl)); in intel_crt_load_detect()
808 intel_de_write(dev_priv, BCLRPAT(dev_priv, cpu_transcoder), in intel_crt_load_detect()
[all …]
A Dintel_pipe_crc.c171 u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X(dev_priv)); in vlv_pipe_crc_ctl_reg()
187 intel_de_write(dev_priv, PORT_DFT2_G4X(dev_priv), tmp); in vlv_pipe_crc_ctl_reg()
233 u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X(dev_priv)); in vlv_undo_pipe_scramble_reset()
250 intel_de_write(dev_priv, PORT_DFT2_G4X(dev_priv), tmp); in vlv_undo_pipe_scramble_reset()
410 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in get_new_crc_ctl_reg()
412 else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv)) in get_new_crc_ctl_reg()
540 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_is_valid_crc_source()
542 else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv)) in intel_is_valid_crc_source()
612 intel_de_write(dev_priv, PIPE_CRC_CTL(dev_priv, pipe), val); in intel_crtc_set_crc_source()
616 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_crtc_set_crc_source()
[all …]
A Dintel_dpio_phy.c364 drm_dbg(&dev_priv->drm, in bxt_dpio_phy_is_enabled()
371 drm_dbg(&dev_priv->drm, in bxt_dpio_phy_is_enabled()
407 dev_priv->display.state.bxt_phy_grc = bxt_get_grc(dev_priv, phy); in _bxt_dpio_phy_init()
415 drm_dbg(&dev_priv->drm, in _bxt_dpio_phy_init()
728 vlv_dpio_get(dev_priv); in chv_set_phy_signal_level()
809 vlv_dpio_put(dev_priv); in chv_set_phy_signal_level()
880 vlv_dpio_get(dev_priv); in chv_phy_pre_pll_enable()
935 vlv_dpio_put(dev_priv); in chv_phy_pre_pll_enable()
949 vlv_dpio_get(dev_priv); in chv_phy_pre_encoder_enable()
1013 vlv_dpio_put(dev_priv); in chv_phy_pre_encoder_enable()
[all …]
/linux/drivers/gpu/drm/vmwgfx/
A Dvmwgfx_drv.c444 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); in vmw_device_init()
455 dev_priv->fifo = vmw_fifo_create(dev_priv); in vmw_device_init()
464 dev_priv->last_read_seqno = vmw_fence_read(dev_priv); in vmw_device_init()
536 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); in vmw_request_device()
862 dev_priv->drm.dev_private = dev_priv; in vmw_driver_load()
942 dev_priv->memory_size -= dev_priv->vram_size; in vmw_driver_load()
975 dev_priv->texture_max_width = vmw_read(dev_priv, in vmw_driver_load()
979 dev_priv->texture_max_height = vmw_read(dev_priv, in vmw_driver_load()
984 dev_priv->max_primary_mem = dev_priv->vram_size; in vmw_driver_load()
994 dev_priv->max_mob_size / 1024, dev_priv->max_mob_pages); in vmw_driver_load()
[all …]
A Dvmwgfx_irq.c144 vmw_update_seqno(dev_priv); in vmw_seqno_passed()
148 if (!vmw_has_fences(dev_priv) && vmw_fifo_idle(dev_priv, seqno)) in vmw_seqno_passed()
187 if (dev_priv->cman) { in vmw_fallback_wait()
249 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); in vmw_generic_waiter_add()
260 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); in vmw_generic_waiter_remove()
279 vmw_generic_waiter_add(dev_priv, vmw_irqflag_fence_goal(dev_priv), in vmw_goal_waiter_add()
285 vmw_generic_waiter_remove(dev_priv, vmw_irqflag_fence_goal(dev_priv), in vmw_goal_waiter_remove()
341 drm_err(&dev_priv->drm, in vmw_irq_install()
352 drm_err(&dev_priv->drm, in vmw_irq_install()
356 dev_priv->irqs[i] = ret; in vmw_irq_install()
[all …]
A Dvmwgfx_cmd.c47 if (!dev_priv->has_mob) in vmw_supports_3d()
103 if (!dev_priv->fifo_mem) in vmw_fifo_create()
131 vmw_fifo_mem_write(dev_priv, SVGA_FIFO_MAX, dev_priv->fifo_mem_size); in vmw_fifo_create()
144 drm_info(&dev_priv->drm, in vmw_fifo_create()
151 drm_warn(&dev_priv->drm, in vmw_fifo_create()
184 dev_priv->fifo = NULL; in vmw_fifo_destroy()
370 if (dev_priv->cman) in vmw_cmd_ctx_reserve()
474 if (dev_priv->cman) in vmw_cmd_commit()
489 if (dev_priv->cman) in vmw_cmd_commit_flush()
506 if (dev_priv->cman) in vmw_cmd_flush()
[all …]
/linux/drivers/gpu/drm/gma500/
A Dpsb_drv.c156 psb_spank(dev_priv); in psb_do_init()
185 if (dev_priv->mmu) { in psb_driver_unload()
190 (dev_priv->mmu), in psb_driver_unload()
247 pg = &dev_priv->gtt; in psb_driver_load()
251 dev_priv->num_pipe = dev_priv->ops->pipes; in psb_driver_load()
255 dev_priv->vdc_reg = in psb_driver_load()
285 dev_priv->aux_reg = dev_priv->vdc_reg; in psb_driver_load()
288 dev_priv->gmbus_reg = dev_priv->aux_reg; in psb_driver_load()
310 dev_priv->gmbus_reg = dev_priv->vdc_reg; in psb_driver_load()
340 if (!dev_priv->mmu) in psb_driver_load()
[all …]
A Dintel_bios.c55 dev_priv->edp.bpp = 18; in parse_edp()
67 dev_priv->edp.bpp = 18; in parse_edp()
70 dev_priv->edp.bpp = 24; in parse_edp()
73 dev_priv->edp.bpp = 30; in parse_edp()
84 dev_priv->edp.pps.t1_t3, dev_priv->edp.pps.t8, in parse_edp()
85 dev_priv->edp.pps.t9, dev_priv->edp.pps.t10, in parse_edp()
92 dev_priv->edp.lanes = 1; in parse_edp()
95 dev_priv->edp.lanes = 2; in parse_edp()
99 dev_priv->edp.lanes = 4; in parse_edp()
103 dev_priv->edp.lanes, dev_priv->edp.rate, dev_priv->edp.bpp); in parse_edp()
[all …]

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