Home
last modified time | relevance | path

Searched refs:display (Results 1 – 25 of 1043) sorted by relevance

12345678910>>...42

/linux/drivers/gpu/drm/xe/
A DMakefile148 -I$(src)/display/ext \
160 $(obj)/i915-display/%.o: $(srctree)/drivers/gpu/drm/i915/display/%.c FORCE
166 display/ext/i915_irq.o \
168 display/intel_fb_bo.o \
170 display/xe_display.o \
173 display/xe_display_wa.o \
174 display/xe_dsb_buffer.o \
175 display/xe_fb_pin.o \
176 display/xe_hdcp_gsc.o \
178 display/xe_tdf.o
[all …]
/linux/drivers/gpu/drm/i915/
A DMakefile220 display/hsw_ips.o \
222 display/i9xx_wm.o \
228 display/intel_bw.o \
256 display/intel_fb.o \
285 display/intel_tc.o \
288 display/intel_wm.o \
307 display/dvo_ivch.o \
311 display/g4x_dp.o \
312 display/g4x_hdmi.o \
313 display/icl_dsi.o \
[all …]
/linux/drivers/gpu/drm/i915/display/
A Dvlv_dsi_regs.h14 #define _MIPI_MMIO_BASE(display) ((display)->dsi.mmio_base) argument
107 #define MIPI_INTR_STAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_STAT,… argument
110 #define MIPI_INTR_EN(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_EN, _MI… argument
209 #define MIPI_HBP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HBP_COUNT,… argument
213 #define MIPI_HFP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HFP_COUNT,… argument
225 #define MIPI_VBP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VBP_COUNT,… argument
229 #define MIPI_VFP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VFP_COUNT,… argument
248 #define MIPI_DPI_DATA(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_DATA, _… argument
254 #define MIPI_INIT_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INIT_COUN… argument
392 #define MIPIA_DBI_TYPEC_CTRL(display) (_MIPI_MMIO_BASE(display) + 0xb100) argument
[all …]
A Dintel_de.h23 intel_dmc_wl_get(display, reg); in __intel_de_read()
27 intel_dmc_wl_put(display, reg); in __intel_de_read()
38 intel_dmc_wl_get(display, reg); in __intel_de_read8()
42 intel_dmc_wl_put(display, reg); in __intel_de_read8()
70 intel_dmc_wl_get(display, reg); in __intel_de_posting_read()
74 intel_dmc_wl_put(display, reg); in __intel_de_posting_read()
81 intel_dmc_wl_get(display, reg); in __intel_de_write()
85 intel_dmc_wl_put(display, reg); in __intel_de_write()
103 intel_dmc_wl_get(display, reg); in __intel_de_rmw()
107 intel_dmc_wl_put(display, reg); in __intel_de_rmw()
[all …]
A Dintel_psr.c395 intel_de_rmw(display, psr_imr_reg(display, cpu_transcoder), in psr_irq_control()
482 intel_de_rmw(display, psr_imr_reg(display, cpu_transcoder), in intel_psr_irq_handler()
717 intel_de_write(display, psr_aux_ctl_reg(display, cpu_transcoder), in hsw_psr_setup_aux()
921 intel_de_rmw(display, psr_ctl_reg(display, cpu_transcoder), in hsw_activate_psr1()
986 intel_de_write(display, EDP_PSR2_CTL(display, cpu_transcoder), in dg2_activate_panel_replay()
1011 if (DISPLAY_VER(display) >= 10 && DISPLAY_VER(display) < 13) in hsw_activate_psr2()
1018 if (DISPLAY_VER(display) >= 12 && DISPLAY_VER(display) < 20) { in hsw_activate_psr2()
1118 intel_de_rmw(display, EDP_PSR2_CTL(display, cpu_transcoder), in psr2_program_idle_frames()
1880 if (HAS_PSR_HW_TRACKING(display) && HAS_PSR2_SEL_FETCH(display)) in intel_psr_enable_source()
2112 intel_de_rmw(display, ALPM_CTL(display, cpu_transcoder), in intel_psr_disable_locked()
[all …]
A Dintel_vrr.c291 intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder), in intel_vrr_set_transcoder_timings()
293 intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder), in intel_vrr_set_transcoder_timings()
301 intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder), in intel_vrr_set_transcoder_timings()
303 intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder), in intel_vrr_set_transcoder_timings()
305 intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), in intel_vrr_set_transcoder_timings()
319 intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), in intel_vrr_send_push()
342 intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), in intel_vrr_enable()
352 intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), in intel_vrr_enable()
356 intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), in intel_vrr_enable()
369 intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), in intel_vrr_disable()
[all …]
A Dintel_pps.c110 drm_dbg_kms(display->drm, in vlv_power_sequencer_kick()
128 pll_enabled = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE; in vlv_power_sequencer_kick()
139 drm_err(display->drm, in vlv_power_sequencer_kick()
281 return intel_de_read(display, PP_STATUS(display, pps_idx)) & PP_ON; in pps_has_pp_on()
286 return intel_de_read(display, PP_CONTROL(display, pps_idx)) & EDP_FORCE_VDD; in pps_has_vdd_on()
722 if (drm_WARN_ON(display->drm, !HAS_DDI(display) && in ilk_get_pp_control()
1697 if (!HAS_DISPLAY(display) || HAS_DDI(display)) in intel_pps_unlock_regs_wa()
1706 intel_de_rmw(display, PP_CONTROL(display, pps_idx), in intel_pps_unlock_regs_wa()
1761 if (drm_WARN_ON(display->drm, HAS_DDI(display))) in assert_pps_unlocked()
1768 port_sel = intel_de_read(display, PP_ON_DELAYS(display, 0)) & in assert_pps_unlocked()
[all …]
A Dintel_opregion.h37 int intel_opregion_setup(struct intel_display *display);
38 void intel_opregion_cleanup(struct intel_display *display);
40 void intel_opregion_register(struct intel_display *display);
41 void intel_opregion_unregister(struct intel_display *display);
43 void intel_opregion_resume(struct intel_display *display);
44 void intel_opregion_suspend(struct intel_display *display,
47 bool intel_opregion_asle_present(struct intel_display *display);
48 void intel_opregion_asle_intr(struct intel_display *display);
51 int intel_opregion_notify_adapter(struct intel_display *display,
56 bool intel_opregion_vbt_present(struct intel_display *display);
[all …]
A Dintel_opregion.c394 if (!HAS_DDI(display)) in intel_opregion_notify_encoder()
474 if (!HAS_DDI(display)) in intel_opregion_notify_adapter()
558 drm_dbg(display->drm, in asle_set_button_array()
561 drm_dbg(display->drm, in asle_set_button_array()
564 drm_dbg(display->drm, in asle_set_button_array()
567 drm_dbg(display->drm, in asle_set_button_array()
570 drm_dbg(display->drm, in asle_set_button_array()
612 struct intel_display *display = opregion->display; in asle_work() local
661 return display->opregion && display->opregion->asle; in intel_opregion_asle_present()
846 drm_dbg(display->drm, in swsci_setup()
[all …]
A Dvlv_dsi.c172 intel_de_write(display, MIPI_INTR_STAT(display, port), in intel_dsi_host_transfer()
346 intel_de_rmw(display, MIPI_CTRL(display, port), in glk_dsi_enable_io()
385 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), in glk_dsi_device_ready()
390 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), in glk_dsi_device_ready()
399 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), in glk_dsi_device_ready()
515 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), in glk_dsi_enter_low_power_mode()
624 intel_de_rmw(display, MIPI_CTRL(display, port), in intel_dsi_port_enable()
1336 intel_de_write(display, MIPI_CTRL(display, PORT_A), in intel_dsi_prepare()
1342 intel_de_write(display, MIPI_CTRL(display, port), in intel_dsi_prepare()
1347 intel_de_rmw(display, MIPI_CTRL(display, port), in intel_dsi_prepare()
[all …]
A Dintel_fbc.c272 struct intel_display *display = fbc->display; in i8xx_fbc_ctl() local
314 struct intel_display *display = fbc->display; in i8xx_fbc_deactivate() local
336 struct intel_display *display = fbc->display; in i8xx_fbc_activate() local
377 struct intel_display *display = fbc->display; in i8xx_fbc_program_cfb() local
440 struct intel_display *display = fbc->display; in g4x_dpfc_ctl() local
463 struct intel_display *display = fbc->display; in g4x_fbc_activate() local
474 struct intel_display *display = fbc->display; in g4x_fbc_deactivate() local
497 struct intel_display *display = fbc->display; in g4x_fbc_program_cfb() local
515 struct intel_display *display = fbc->display; in ilk_fbc_activate() local
526 struct intel_display *display = fbc->display; in ilk_fbc_deactivate() local
[all …]
A Dintel_bios.c504 drm_err(display->drm, in init_bdb_block()
1805 drm_err(display->drm, in find_panel_sequence_block()
2428 struct intel_display *display = devdata->display; in intel_bios_encoder_port() local
2499 struct intel_display *display = devdata->display; in sanitize_device_type() local
2520 struct intel_display *display = devdata->display; in sanitize_hdmi_level_shift() local
2634 struct intel_display *display = devdata->display; in print_ddi_port() local
2705 struct intel_display *display = devdata->display; in parse_ddi_port() local
2845 devdata->display = display; in parse_general_definitions()
2884 display->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(display, in init_vbt_defaults()
2929 devdata->display = display; in init_vbt_missing_defaults()
[all …]
A Dintel_dmc_wl.c57 struct intel_dmc_wl *wl = &display->wl; in __intel_dmc_wl_release()
69 struct intel_display *display = in intel_dmc_wl_work() local
114 if (DISPLAY_VER(display) < 20 || in __intel_dmc_wl_supported()
116 !display->params.enable_dmc_wl) in __intel_dmc_wl_supported()
124 struct intel_dmc_wl *wl = &display->wl; in intel_dmc_wl_init()
127 if (DISPLAY_VER(display) < 20 || !display->params.enable_dmc_wl) in intel_dmc_wl_init()
137 struct intel_dmc_wl *wl = &display->wl; in intel_dmc_wl_enable()
140 if (!__intel_dmc_wl_supported(display)) in intel_dmc_wl_enable()
164 struct intel_dmc_wl *wl = &display->wl; in intel_dmc_wl_disable()
167 if (!__intel_dmc_wl_supported(display)) in intel_dmc_wl_disable()
[all …]
A Dintel_quirks.c14 display->quirks.mask |= BIT(quirk); in intel_set_quirk()
27 intel_set_quirk(display, QUIRK_LVDS_SSC_DISABLE); in quirk_ssc_force_disable()
37 intel_set_quirk(display, QUIRK_INVERT_BRIGHTNESS); in quirk_invert_brightness()
44 intel_set_quirk(display, QUIRK_BACKLIGHT_PRESENT); in quirk_backlight_present()
53 intel_set_quirk(display, QUIRK_INCREASE_T12_DELAY); in quirk_increase_t12_delay()
54 drm_info(display->drm, "Applying T12 delay quirk\n"); in quirk_increase_t12_delay()
85 void (*hook)(struct intel_display *display);
105 void (*hook)(struct intel_display *display);
259 q->hook(display); in intel_init_quirks()
263 intel_dmi_quirks[i].hook(display); in intel_init_quirks()
[all …]
A Dintel_display_driver.c207 struct intel_display *display = &i915->display; in intel_display_driver_probe_noirq() local
220 intel_bios_init(display); in intel_display_driver_probe_noirq()
266 intel_init_quirks(display); in intel_display_driver_probe_noirq()
268 intel_fbc_init(display); in intel_display_driver_probe_noirq()
419 struct intel_display *display = &i915->display; in intel_display_driver_probe_nogem() local
431 intel_pps_setup(display); in intel_display_driver_probe_nogem()
456 intel_hti_init(display); in intel_display_driver_probe_nogem()
530 struct intel_display *display = &i915->display; in intel_display_driver_register() local
583 struct intel_display *display = &i915->display; in intel_display_driver_remove_noirq() local
620 struct intel_display *display = &i915->display; in intel_display_driver_remove_nogem() local
[all …]
A Dintel_hdmi.c71 drm_WARN(display->drm, in assert_hdmi_port_disabled()
80 drm_WARN(display->drm, in assert_hdmi_transcoder_func_disabled()
81 intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & in assert_hdmi_transcoder_func_disabled()
444 intel_de_write(display, in vlv_write_infoframe()
450 intel_de_write(display, in vlv_write_infoframe()
984 if (HAS_DDI(display)) in intel_hdmi_set_gcp_infoframe()
1010 if (HAS_DDI(display)) in intel_hdmi_read_gcp_infoframe()
1488 drm_err(display->drm, in kbl_repositioning_enc_en_signal()
1496 drm_err(display->drm, in kbl_repositioning_enc_en_signal()
2621 if (HAS_DDI(display)) in intel_hdmi_connector_atomic_check()
[all …]
A Dintel_vblank.c106 frame = intel_de_read64_2x32(display, PIPEFRAMEPIXEL(display, pipe), in i915_get_vblank_counter()
107 PIPEFRAME(display, pipe)); in i915_get_vblank_counter()
129 return intel_de_read(display, PIPE_FRMCOUNT_G4X(display, pipe)); in g4x_get_vblank_counter()
224 if (DISPLAY_VER(display) == 2) in intel_crtc_scanline_offset()
252 position = intel_de_read_fw(display, PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK; in __intel_get_crtc_scanline()
271 temp = intel_de_read_fw(display, in __intel_get_crtc_scanline()
339 drm_dbg(display->drm, in i915_get_crtc_scanoutpos()
425 intel_vblank_section_exit(display); in i915_get_crtc_scanoutpos()
495 drm_err(display->drm, in wait_for_pipe_scanline_moving()
523 drm_WARN_ON(display->drm, in intel_crtc_update_active_timings()
[all …]
A Dintel_frontbuffer.c86 struct intel_display *display = &i915->display; in frontbuffer_flush() local
89 spin_lock(&i915->display.fb_tracking.lock); in frontbuffer_flush()
91 spin_unlock(&i915->display.fb_tracking.lock); in frontbuffer_flush()
120 spin_lock(&i915->display.fb_tracking.lock); in intel_frontbuffer_flip_prepare()
124 spin_unlock(&i915->display.fb_tracking.lock); in intel_frontbuffer_flip_prepare()
140 spin_lock(&i915->display.fb_tracking.lock); in intel_frontbuffer_flip_complete()
164 spin_lock(&i915->display.fb_tracking.lock); in intel_frontbuffer_flip()
177 struct intel_display *display = &i915->display; in __intel_fb_invalidate() local
180 spin_lock(&i915->display.fb_tracking.lock); in __intel_fb_invalidate()
201 spin_lock(&i915->display.fb_tracking.lock); in __intel_fb_flush()
[all …]
A Dintel_hotplug.c266 display.hotplug.reenable_work.work); in intel_hpd_irq_storm_reenable_work()
412 queue_work(i915->display.hotplug.dp_wq, &i915->display.hotplug.dig_port_work); in intel_hpd_trigger_irq()
422 display.hotplug.hotplug_work.work); in i915_hotplug_work_func()
437 dev_priv->display.hotplug.event_bits = 0; in i915_hotplug_work_func()
439 dev_priv->display.hotplug.retry_bits = 0; in i915_hotplug_work_func()
641 queue_work(dev_priv->display.hotplug.dp_wq, &dev_priv->display.hotplug.dig_port_work); in intel_hpd_irq_handler()
731 display.hotplug.poll_init_work); in i915_hpd_poll_init_work()
905 dev_priv->display.hotplug.event_bits = 0; in intel_hpd_cancel_work()
906 dev_priv->display.hotplug.retry_bits = 0; in intel_hpd_cancel_work()
954 if (i915->display.hotplug.event_bits || in queue_work_for_missed_irqs()
[all …]
A Dintel_lspcon.c88 drm_err(display->drm, "Can't read description\n"); in lspcon_detect_vendor()
99 drm_dbg_kms(display->drm, "Vendor: Mega Chips\n"); in lspcon_detect_vendor()
104 drm_dbg_kms(display->drm, "Vendor: Parade Tech\n"); in lspcon_detect_vendor()
137 drm_dbg_kms(display->drm, "LSPCON capable of HDR\n"); in lspcon_detect_hdr_capability()
188 drm_dbg_kms(display->drm, "Current LSPCON mode %s\n", in lspcon_wait_mode()
233 drm_dbg_kms(display->drm, "Native AUX CH down\n"); in lspcon_wake_native_aux_ch()
272 drm_dbg_kms(display->drm, "LSPCON detected\n"); in lspcon_probe()
586 drm_err(display->drm, "Failed to pack AVI IF\n"); in lspcon_set_infoframes()
643 tmp = intel_de_read(display, in lspcon_infoframes_enabled()
670 drm_err(display->drm, "Failed to probe lspcon\n"); in lspcon_init()
[all …]
A Dintel_hti.c12 void intel_hti_init(struct intel_display *display) in intel_hti_init() argument
18 if (DISPLAY_INFO(display)->has_hti) in intel_hti_init()
19 display->hti.state = intel_de_read(display, HDPORT_STATE); in intel_hti_init()
22 bool intel_hti_uses_phy(struct intel_display *display, enum phy phy) in intel_hti_uses_phy() argument
24 if (drm_WARN_ON(display->drm, phy == PHY_NONE)) in intel_hti_uses_phy()
27 return display->hti.state & HDPORT_ENABLED && in intel_hti_uses_phy()
28 display->hti.state & HDPORT_DDI_USED(phy); in intel_hti_uses_phy()
31 u32 intel_hti_dpll_mask(struct intel_display *display) in intel_hti_dpll_mask() argument
33 if (!(display->hti.state & HDPORT_ENABLED)) in intel_hti_dpll_mask()
40 return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, display->hti.state); in intel_hti_dpll_mask()
A Dintel_wm.c47 if (i915->display.funcs.wm->update_wm) in intel_update_watermarks()
48 i915->display.funcs.wm->update_wm(i915); in intel_update_watermarks()
56 if (i915->display.funcs.wm->compute_pipe_wm) in intel_compute_pipe_wm()
119 if (i915->display.funcs.wm->get_hw_state) in intel_wm_get_hw_state()
219 latencies = dev_priv->display.wm.skl_latency; in pri_wm_latency_show()
221 latencies = dev_priv->display.wm.pri_latency; in pri_wm_latency_show()
234 latencies = dev_priv->display.wm.skl_latency; in spr_wm_latency_show()
236 latencies = dev_priv->display.wm.spr_latency; in spr_wm_latency_show()
249 latencies = dev_priv->display.wm.skl_latency; in cur_wm_latency_show()
251 latencies = dev_priv->display.wm.cur_latency; in cur_wm_latency_show()
[all …]
A Dintel_sprite.c820 intel_de_write_fw(display, SPRPOS(pipe), in ivb_sprite_update_noarm()
1157 intel_de_write_fw(display, DVSPOS(pipe), in g4x_sprite_update_noarm()
1292 drm_dbg_kms(display->drm, in g4x_sprite_check_scaling()
1305 drm_dbg_kms(display->drm, in g4x_sprite_check_scaling()
1312 drm_dbg_kms(display->drm, in g4x_sprite_check_scaling()
1319 drm_dbg_kms(display->drm, in g4x_sprite_check_scaling()
1340 if (DISPLAY_VER(display) < 7) { in g4x_sprite_check()
1369 if (DISPLAY_VER(display) >= 7) in g4x_sprite_check()
1388 drm_dbg_kms(display->drm, in chv_plane_check_rotation()
1590 struct intel_display *display = &dev_priv->display; in intel_sprite_plane_create() local
[all …]
A Dg4x_dp.c184 struct intel_display *display = &dev_priv->display; in assert_edp_pll() local
216 intel_de_posting_read(display, DP_A); in ilk_edp_pll_on()
231 intel_de_posting_read(display, DP_A); in ilk_edp_pll_on()
258 struct intel_display *display = &dev_priv->display; in cpt_dp_port_selected() local
261 for_each_pipe(display, p) { in cpt_dp_port_selected()
283 struct intel_display *display = &dev_priv->display; in g4x_dp_port_enabled() local
427 if (drm_WARN_ON(display->drm, in intel_dp_link_down()
432 drm_dbg_kms(display->drm, "\n"); in intel_dp_link_down()
1224 return intel_de_read(display, PORT_HOTPLUG_STAT(display)) & bit; in g4x_digital_port_connected()
1294 struct intel_display *display = &dev_priv->display; in g4x_dp_init() local
[all …]
/linux/Documentation/devicetree/bindings/display/
A Dallwinner,sun4i-a10-display-engine.yaml4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-engine.yaml#
52 - allwinner,sun4i-a10-display-engine
54 - allwinner,sun5i-a13-display-engine
55 - allwinner,sun6i-a31-display-engine
57 - allwinner,sun7i-a20-display-engine
58 - allwinner,sun8i-a23-display-engine
59 - allwinner,sun8i-a33-display-engine
61 - allwinner,sun8i-h3-display-engine
62 - allwinner,sun8i-r40-display-engine
63 - allwinner,sun8i-v3s-display-engine
[all …]

Completed in 95 milliseconds

12345678910>>...42