Searched refs:div4 (Results 1 – 9 of 9) sorted by relevance
| /linux/Documentation/devicetree/bindings/clock/ |
| A D | tesla,fsd-clock.yaml | 91 - description: Shared0 PLL div4 clock (from CMU_CMU)
95 - description: PERIC shared1 div4 DMAclock (from CMU_CMU)
116 - description: FSYS0 shared1 div4 clock (from CMU_CMU)
117 - description: FSYS0 shared0 div4 clock (from CMU_CMU)
136 - description: FSYS1 shared0 div4 clock (from CMU_CMU)
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| A D | amlogic,s4-peripherals-clkc.yaml | 26 - description: input fixed pll div4
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| /linux/Documentation/devicetree/bindings/clock/ti/davinci/ |
| A D | da8xx-cfgchip.txt | 43 - clock-names: shall be "pll0_sysclk3", "div4.5"
71 div4p5_clk: div4.5 {
81 clock-names = "pll0_sysclk3", "div4.5";
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| /linux/drivers/clk/uniphier/ |
| A D | clk-uniphier.h | 122 #define UNIPHIER_CLK_DIV5(parent, div0, div1, div2, div3, div4) \ argument
124 UNIPHIER_CLK_DIV(parent, div4)
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| /linux/arch/arm/boot/dts/ti/davinci/ |
| A D | da850.dtsi | 400 div4p5_clk: div4.5 {
410 clock-names = "pll0_sysclk3", "div4.5";
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| /linux/arch/arm/boot/dts/ti/omap/ |
| A D | am33xx-clocks.dtsi | 316 dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm {
325 dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 {
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| A D | am43xx-clocks.dtsi | 370 dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm {
379 dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 {
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| /linux/arch/arm64/boot/dts/qcom/ |
| A D | msm8996-oneplus-common.dtsi | 43 divclk4: div4-clk {
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| /linux/drivers/video/fbdev/ |
| A D | amifb.c | 551 #define div4(v) ((v)>>2) macro
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