| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| A D | display_rq_dlg_helpers.c | 197 dlg_regs->refcyc_h_blank_end); in print__dlg_regs_st()
200 dlg_regs->dlg_vblank_end); in print__dlg_regs_st()
206 dlg_regs->refcyc_per_htotal); in print__dlg_regs_st()
212 dlg_regs->dst_y_after_scaler); in print__dlg_regs_st()
215 dlg_regs->dst_y_prefetch); in print__dlg_regs_st()
218 dlg_regs->dst_y_per_vm_vblank); in print__dlg_regs_st()
224 dlg_regs->dst_y_per_vm_flip); in print__dlg_regs_st()
227 dlg_regs->dst_y_per_row_flip); in print__dlg_regs_st()
233 dlg_regs->vratio_prefetch); in print__dlg_regs_st()
236 dlg_regs->vratio_prefetch_c); in print__dlg_regs_st()
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| A D | display_mode_lib.h | 53 display_dlg_regs_st *dlg_regs,
71 display_dlg_regs_st *dlg_regs,
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| A D | dml1_display_rq_dlg_calc.h | 56 struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
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| A D | display_rq_dlg_helpers.h | 43 …lg_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_dlg_regs_st *dlg_regs);
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | display_rq_dlg_calc_32.c | 207 display_dlg_regs_st *dlg_regs, in dml32_rq_dlg_get_dlg_reg() argument
266 memset(dlg_regs, 0, sizeof(*dlg_regs)); in dml32_rq_dlg_get_dlg_reg()
290 dlg_regs->vready_after_vcount0 = vready_after_vcount0; in dml32_rq_dlg_get_dlg_reg()
525 dlg_regs->chunk_hdl_adjust_cur0 = 3; in dml32_rq_dlg_get_dlg_reg()
526 dlg_regs->dst_y_offset_cur0 = 0; in dml32_rq_dlg_get_dlg_reg()
527 dlg_regs->chunk_hdl_adjust_cur1 = 3; in dml32_rq_dlg_get_dlg_reg()
528 dlg_regs->dst_y_offset_cur1 = 0; in dml32_rq_dlg_get_dlg_reg()
530 dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off in dml32_rq_dlg_get_dlg_reg()
569 dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1; in dml32_rq_dlg_get_dlg_reg()
571 ASSERT(dlg_regs->dst_y_after_scaler < (unsigned int) 8); in dml32_rq_dlg_get_dlg_reg()
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| A D | display_rq_dlg_calc_32.h | 64 display_dlg_regs_st *dlg_regs,
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| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_hw_sequencer_debug.c | 261 …pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_… in dcn10_get_dlg_states()
262 dlg_regs->refcyc_per_htotal, dlg_regs->refcyc_x_after_scaler, dlg_regs->dst_y_after_scaler, in dcn10_get_dlg_states()
263 dlg_regs->dst_y_prefetch, dlg_regs->dst_y_per_vm_vblank, dlg_regs->dst_y_per_row_vblank, in dcn10_get_dlg_states()
264 dlg_regs->dst_y_per_vm_flip, dlg_regs->dst_y_per_row_flip, dlg_regs->ref_freq_to_pix_freq, in dcn10_get_dlg_states()
265 dlg_regs->vratio_prefetch, dlg_regs->vratio_prefetch_c, dlg_regs->refcyc_per_pte_group_vblank_l, in dcn10_get_dlg_states()
269 dlg_regs->refcyc_per_meta_chunk_flip_c, dlg_regs->dst_y_per_pte_row_nom_l, in dcn10_get_dlg_states()
270 dlg_regs->dst_y_per_pte_row_nom_c, dlg_regs->refcyc_per_pte_group_nom_l, in dcn10_get_dlg_states()
271 dlg_regs->refcyc_per_pte_group_nom_c, dlg_regs->dst_y_per_meta_row_nom_l, in dcn10_get_dlg_states()
275 …dlg_regs->refcyc_per_line_delivery_c, dlg_regs->chunk_hdl_adjust_cur0, dlg_regs->dst_y_offset_cur1, in dcn10_get_dlg_states()
276 … dlg_regs->chunk_hdl_adjust_cur1, dlg_regs->vready_after_vcount0, dlg_regs->dst_y_delta_drq_limit, in dcn10_get_dlg_states()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| A D | dml21_utils.c | 177 memset(&out->dlg_regs, 0, sizeof(out->dlg_regs)); in dml21_update_pipe_ctx_dchub_regs()
179 out->dlg_regs.dlg_vblank_end = disp_dlg_regs->dlg_vblank_end; in dml21_update_pipe_ctx_dchub_regs()
181 out->dlg_regs.refcyc_per_htotal = disp_dlg_regs->refcyc_per_htotal; in dml21_update_pipe_ctx_dchub_regs()
184 out->dlg_regs.dst_y_prefetch = disp_dlg_regs->dst_y_prefetch; in dml21_update_pipe_ctx_dchub_regs()
187 out->dlg_regs.dst_y_per_vm_flip = disp_dlg_regs->dst_y_per_vm_flip; in dml21_update_pipe_ctx_dchub_regs()
190 out->dlg_regs.vratio_prefetch = disp_dlg_regs->vratio_prefetch; in dml21_update_pipe_ctx_dchub_regs()
191 out->dlg_regs.vratio_prefetch_c = disp_dlg_regs->vratio_prefetch_c; in dml21_update_pipe_ctx_dchub_regs()
217 out->dlg_regs.dst_y_offset_cur0 = disp_dlg_regs->dst_y_offset_cur0; in dml21_update_pipe_ctx_dchub_regs()
224 out->dlg_regs.dmdata_dl_delta = disp_dlg_regs->dmdata_dl_delta; in dml21_update_pipe_ctx_dchub_regs()
313 &pln_prog->phantom_plane.pipe_regs[pipe_reg_index]->dlg_regs, in dml21_program_dc_pipe()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | display_mode_util.c | 249 void dml_print_dlg_regs_st(const dml_display_dlg_regs_st *dlg_regs) in dml_print_dlg_regs_st() argument
253 dml_print("DML: refcyc_h_blank_end = 0x%x\n", dlg_regs->refcyc_h_blank_end); in dml_print_dlg_regs_st()
254 dml_print("DML: dlg_vblank_end = 0x%x\n", dlg_regs->dlg_vblank_end); in dml_print_dlg_regs_st()
256 dml_print("DML: refcyc_per_htotal = 0x%x\n", dlg_regs->refcyc_per_htotal); in dml_print_dlg_regs_st()
258 dml_print("DML: dst_y_after_scaler = 0x%x\n", dlg_regs->dst_y_after_scaler); in dml_print_dlg_regs_st()
259 dml_print("DML: dst_y_prefetch = 0x%x\n", dlg_regs->dst_y_prefetch); in dml_print_dlg_regs_st()
262 dml_print("DML: dst_y_per_vm_flip = 0x%x\n", dlg_regs->dst_y_per_vm_flip); in dml_print_dlg_regs_st()
263 dml_print("DML: dst_y_per_row_flip = 0x%x\n", dlg_regs->dst_y_per_row_flip); in dml_print_dlg_regs_st()
265 dml_print("DML: vratio_prefetch = 0x%x\n", dlg_regs->vratio_prefetch); in dml_print_dlg_regs_st()
266 dml_print("DML: vratio_prefetch_c = 0x%x\n", dlg_regs->vratio_prefetch_c); in dml_print_dlg_regs_st()
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| A D | dml2_translation_helper.c | 1434 memset(&out->dlg_regs, 0, sizeof(out->dlg_regs)); in dml2_update_pipe_ctx_dchub_regs()
1435 out->dlg_regs.refcyc_h_blank_end = disp_dlg_regs->refcyc_h_blank_end; in dml2_update_pipe_ctx_dchub_regs()
1436 out->dlg_regs.dlg_vblank_end = disp_dlg_regs->dlg_vblank_end; in dml2_update_pipe_ctx_dchub_regs()
1438 out->dlg_regs.refcyc_per_htotal = disp_dlg_regs->refcyc_per_htotal; in dml2_update_pipe_ctx_dchub_regs()
1441 out->dlg_regs.dst_y_prefetch = disp_dlg_regs->dst_y_prefetch; in dml2_update_pipe_ctx_dchub_regs()
1444 out->dlg_regs.dst_y_per_vm_flip = disp_dlg_regs->dst_y_per_vm_flip; in dml2_update_pipe_ctx_dchub_regs()
1447 out->dlg_regs.vratio_prefetch = disp_dlg_regs->vratio_prefetch; in dml2_update_pipe_ctx_dchub_regs()
1448 out->dlg_regs.vratio_prefetch_c = disp_dlg_regs->vratio_prefetch_c; in dml2_update_pipe_ctx_dchub_regs()
1473 out->dlg_regs.dst_y_offset_cur0 = disp_dlg_regs->dst_y_offset_cur0; in dml2_update_pipe_ctx_dchub_regs()
1475 out->dlg_regs.dst_y_offset_cur1 = disp_dlg_regs->dst_y_offset_cur1; in dml2_update_pipe_ctx_dchub_regs()
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| A D | dml_display_rq_dlg_calc.h | 55 void dml_rq_dlg_get_dlg_reg(dml_display_dlg_regs_st *dlg_regs,
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| A D | display_mode_util.h | 56 __DML_DLL_EXPORT__ void dml_print_dlg_regs_st(const dml_display_dlg_regs_st *dlg_regs);
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| A D | dcn10_hwseq.c | 246 …pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_… in dcn10_log_hubp_states()
247 dlg_regs->refcyc_per_htotal, dlg_regs->refcyc_x_after_scaler, dlg_regs->dst_y_after_scaler, in dcn10_log_hubp_states()
248 dlg_regs->dst_y_prefetch, dlg_regs->dst_y_per_vm_vblank, dlg_regs->dst_y_per_row_vblank, in dcn10_log_hubp_states()
249 dlg_regs->dst_y_per_vm_flip, dlg_regs->dst_y_per_row_flip, dlg_regs->ref_freq_to_pix_freq, in dcn10_log_hubp_states()
250 dlg_regs->vratio_prefetch, dlg_regs->vratio_prefetch_c, dlg_regs->refcyc_per_pte_group_vblank_l, in dcn10_log_hubp_states()
254 dlg_regs->refcyc_per_meta_chunk_flip_c, dlg_regs->dst_y_per_pte_row_nom_l, in dcn10_log_hubp_states()
255 dlg_regs->dst_y_per_pte_row_nom_c, dlg_regs->refcyc_per_pte_group_nom_l, in dcn10_log_hubp_states()
256 dlg_regs->refcyc_per_pte_group_nom_c, dlg_regs->dst_y_per_meta_row_nom_l, in dcn10_log_hubp_states()
260 …dlg_regs->refcyc_per_line_delivery_c, dlg_regs->chunk_hdl_adjust_cur0, dlg_regs->dst_y_offset_cur1, in dcn10_log_hubp_states()
261 … dlg_regs->chunk_hdl_adjust_cur1, dlg_regs->vready_after_vcount0, dlg_regs->dst_y_delta_drq_limit, in dcn10_log_hubp_states()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | display_rq_dlg_calc_20v2.h | 62 display_dlg_regs_st *dlg_regs,
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| A D | display_rq_dlg_calc_20.h | 62 display_dlg_regs_st *dlg_regs,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| A D | display_rq_dlg_calc_21.h | 62 display_dlg_regs_st *dlg_regs,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| A D | display_rq_dlg_calc_30.h | 58 display_dlg_regs_st *dlg_regs,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | display_rq_dlg_calc_31.h | 58 display_dlg_regs_st *dlg_regs,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| A D | display_rq_dlg_calc_314.h | 59 display_dlg_regs_st *dlg_regs,
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| A D | hubp.h | 142 struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
149 struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
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| A D | mem_input.h | 107 struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/ |
| A D | dml_top_dchub_registers.h | 148 struct dml2_display_dlg_regs dlg_regs; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| A D | dcn_calcs.c | 459 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &pipe->dlg_regs; in dcn_bw_calc_rq_dlg_ttu() local
470 memset(dlg_regs, 0, sizeof(*dlg_regs)); in dcn_bw_calc_rq_dlg_ttu()
511 dlg_regs, in dcn_bw_calc_rq_dlg_ttu()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| A D | core_types.h | 454 struct _vcs_dpi_display_dlg_regs_st dlg_regs; member
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| A D | dcn20_hwseq.c | 1594 struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs; in dcn20_detect_pipe_changes()
1596 struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs; in dcn20_detect_pipe_changes()
1639 if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) || in dcn20_detect_pipe_changes()
1682 &pipe_ctx->dlg_regs, in dcn20_update_dchubp_dpp()
1694 &pipe_ctx->dlg_regs, in dcn20_update_dchubp_dpp()
2440 pipe_ctx->dlg_regs.min_dst_y_next_start); in dcn20_optimize_bandwidth()
2489 &pipe_ctx->dlg_regs, in dcn20_update_bandwidth()
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