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Searched refs:dml (Results 1 – 25 of 51) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/dml/
A DMakefile39 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
40 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_ccflags)
41 CFLAGS_$(AMDDALPATH)/dc/dml/dcn10/dcn10_fpu.o := $(dml_ccflags)
42 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/dcn20_fpu.o := $(dml_ccflags)
56 CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/dcn30_fpu.o := $(dml_ccflags)
57 CFLAGS_$(AMDDALPATH)/dc/dml/dcn32/dcn32_fpu.o := $(dml_ccflags)
62 CFLAGS_$(AMDDALPATH)/dc/dml/dcn35/dcn35_fpu.o := $(dml_ccflags)
64 CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/dcn31_fpu.o := $(dml_ccflags)
68 CFLAGS_$(AMDDALPATH)/dc/dml/dsc/rc_calc_fpu.o := $(dml_ccflags)
69 CFLAGS_$(AMDDALPATH)/dc/dml/calcs/dcn_calcs.o := $(dml_ccflags)
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/
A Ddml_top.c30 memset(dml, 0, sizeof(struct dml2_instance)); in dml2_initialize_instance()
35 dml->project_id = in_out->options.project_id; in dml2_initialize_instance()
36 dml->pmo_options = in_out->options.pmo_options; in dml2_initialize_instance()
73 pmo_init_params.soc_bb = &dml->soc_bbox; in dml2_initialize_instance()
74 pmo_init_params.ip_caps = &dml->ip_caps; in dml2_initialize_instance()
118 .dml = dml, in dml2_check_mode_supported()
197 l->min_clock_for_latency_phase.dml = dml; in dml2_build_mode_programming()
214 l->mcache_phase.dml = dml; in dml2_build_mode_programming()
240 l->uclk_pstate_phase.dml = dml; in dml2_build_mode_programming()
259 l->vmin_phase.dml = dml; in dml2_build_mode_programming()
[all …]
A Ddml2_top_optimization.c51 l->test_mcache.calc_mcache_count_params.dml2_instance = params->dml; in dml2_top_optimization_test_function_mcache()
101 l->vmin.init_params.instance = &params->dml->pmo_instance; in dml2_top_optimization_init_function_vmin()
138 if (!params->dml || in dml2_top_optimization_perform_optimization_phase()
148 init_params.dml = params->dml; in dml2_top_optimization_perform_optimization_phase()
155 test_params.dml = params->dml; in dml2_top_optimization_perform_optimization_phase()
164 optimize_params.dml = params->dml; in dml2_top_optimization_perform_optimization_phase()
172 l->mode_support_params.instance = &params->dml->core_instance; in dml2_top_optimization_perform_optimization_phase()
189 test_params.dml = params->dml; in dml2_top_optimization_perform_optimization_phase()
212 if (!params->dml || in dml2_top_optimization_perform_optimization_phase_1()
226 l->mode_support_params.instance = &params->dml->core_instance; in dml2_top_optimization_perform_optimization_phase_1()
[all …]
A Ddml_top_mcache.c201 struct dml2_instance *dml = (struct dml2_instance *)params->dml2_instance; in dml2_top_mcache_validate_admissability() local
202 …struct dml2_top_mcache_validate_admissability_locals *l = &dml->scratch.mcache_validate_admissabil… in dml2_top_mcache_validate_admissability()
506 struct dml2_instance *dml = (struct dml2_instance *)params->dml2_instance; in dml2_top_mcache_calc_mcache_count_and_offsets() local
507 …struct dml2_top_mcache_verify_mcache_size_locals *l = &dml->scratch.mcache_verify_mcache_size_loca… in dml2_top_mcache_calc_mcache_count_and_offsets()
513 if (dml->soc_bbox.num_dcc_mcaches == 0) { in dml2_top_mcache_calc_mcache_count_and_offsets()
518 l->calc_mcache_params.instance = &dml->core_instance; in dml2_top_mcache_calc_mcache_count_and_offsets()
529 if (!dml->core_instance.calculate_mcache_allocation(&l->calc_mcache_params)) { in dml2_top_mcache_calc_mcache_count_and_offsets()
542 if (total_mcaches_required > dml->soc_bbox.num_dcc_mcaches) { in dml2_top_mcache_calc_mcache_count_and_offsets()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddcn30_fpu.c294 if (dc->dml.ip.writeback_max_hscl_taps > 1) { in dcn30_fpu_populate_dml_writeback_from_context()
348 struct display_mode_lib *dml, in dcn30_fpu_set_mcif_arb_params() argument
419 maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; in dcn30_fpu_calculate_wm_and_dlg()
420 dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn30_fpu_calculate_wm_and_dlg()
425 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk) in dcn30_fpu_calculate_wm_and_dlg()
426 dcfclk = context->bw_ctx.dml.soc.min_dcfclk; in dcn30_fpu_calculate_wm_and_dlg()
574 dc->dml.soc.num_chans <= 4 && in dcn30_fpu_calculate_wm_and_dlg()
575 context->bw_ctx.dml.vba.DRAMSpeed <= 1700 && in dcn30_fpu_calculate_wm_and_dlg()
576 context->bw_ctx.dml.vba.DRAMSpeed >= 1500) { in dcn30_fpu_calculate_wm_and_dlg()
578 for (i = 0; i < dc->dml.soc.num_states; i++) { in dcn30_fpu_calculate_wm_and_dlg()
[all …]
A Ddcn30_fpu.h39 struct display_mode_lib *dml,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/
A Ddcn301_fpu.c295 struct display_mode_lib *dml, in calculate_wm_set_for_vlevel() argument
301 ASSERT(vlevel < dml->soc.num_states); in calculate_wm_set_for_vlevel()
304 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()
305 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; in calculate_wm_set_for_vlevel()
307 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; in calculate_wm_set_for_vlevel()
308 dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us; in calculate_wm_set_for_vlevel()
311 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
435 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_fpu_calculate_wm_and_dlg()
440 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_fpu_calculate_wm_and_dlg()
445 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_fpu_calculate_wm_and_dlg()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
A Ddcn31_fpu.c471 …if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[context->bw_ctx.dml.vba.VoltageLevel][context->… in dcn315_update_soc_for_wm_a()
472 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latenc… in dcn315_update_soc_for_wm_a()
475 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = in dcn315_update_soc_for_wm_a()
477 context->bw_ctx.dml.soc.sr_exit_time_us = in dcn315_update_soc_for_wm_a()
489 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn31_calculate_wm_and_dlg_fp()
494 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk) in dcn31_calculate_wm_and_dlg_fp()
495 dcfclk = context->bw_ctx.dml.soc.min_dcfclk; in dcn31_calculate_wm_and_dlg_fp()
562 …context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_d… in dcn31_calculate_wm_and_dlg_fp()
665 dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31); in dcn31_update_bw_bounding_box()
798 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2; in dcn316_update_bw_bounding_box()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddcn20_fpu.c1165 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] in dcn20_calculate_dlg_params()
1226 …bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] … in dcn20_calculate_dlg_params()
1235 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml, in dcn20_calculate_dlg_params()
1245 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml, in dcn20_calculate_dlg_params()
1751 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; in dcn20_calculate_wm()
1760 …context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from… in dcn20_calculate_wm()
2067 …dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_st… in dcn20_validate_bandwidth_internal()
2113 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latenc… in dcn20_validate_bandwidth_fp()
2210 struct display_mode_lib *dml, in calculate_wm_set_for_vlevel() argument
2216 ASSERT(vlevel < dml->soc.num_states); in calculate_wm_set_for_vlevel()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddcn32_fpu.c479 …unsigned int dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcCo… in dcn32_set_phantom_stream_timing()
1415 context->bw_ctx.dml.vba.VoltageLevel = *vlevel; in try_odm_power_optimization_and_revalidate()
1662 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] in dcn32_calculate_dlg_params()
1673 …if (context->bw_ctx.dml.vba.FCLKChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_fc… in dcn32_calculate_dlg_params()
1678 …usr_retraining_support = context->bw_ctx.dml.vba.USRRetrainingSupport[vlevel][context->bw_ctx.dml.… in dcn32_calculate_dlg_params()
1795 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg_v2(&context->bw_ctx.dml, in dcn32_calculate_dlg_params()
2146 int vlevel = context->bw_ctx.dml.soc.num_states; in dcn32_internal_validate_bw()
2305 …double dcfclk_from_validation = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vb… in dcn32_calculate_wm_and_dlg_fpu()
2308 …bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.ma… in dcn32_calculate_wm_and_dlg_fpu()
2394 …cfclk_from_fw_based_mclk_switching = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.d… in dcn32_calculate_wm_and_dlg_fpu()
[all …]
/linux/net/packet/
A Ddiag.c49 struct packet_diag_mclist *dml; in pdiag_put_mclist() local
51 dml = nla_reserve_nohdr(nlskb, sizeof(*dml)); in pdiag_put_mclist()
52 if (!dml) { in pdiag_put_mclist()
58 dml->pdmc_index = ml->ifindex; in pdiag_put_mclist()
59 dml->pdmc_type = ml->type; in pdiag_put_mclist()
60 dml->pdmc_alen = ml->alen; in pdiag_put_mclist()
61 dml->pdmc_count = ml->count; in pdiag_put_mclist()
62 BUILD_BUG_ON(sizeof(dml->pdmc_addr) != sizeof(ml->addr)); in pdiag_put_mclist()
63 memcpy(dml->pdmc_addr, ml->addr, sizeof(ml->addr)); in pdiag_put_mclist()
/linux/drivers/gpu/drm/amd/display/dc/dml/calcs/
A Ddcn_calcs.c458 struct display_mode_lib *dml = (struct display_mode_lib *)(&dc->dml); in dcn_bw_calc_rq_dlg_ttu() local
508 dml1_extract_rq_regs(dml, rq_regs, rq_param); in dcn_bw_calc_rq_dlg_ttu()
510 dml, in dcn_bw_calc_rq_dlg_ttu()
1294 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = in dcn_validate_bandwidth()
1704 dc->dml.soc.ideal_dram_bw_after_urgent_percent = in dcn_bw_sync_calcs_and_dml()
1708 dc->dml.soc.round_trip_ping_latency_dcfclk_cycles = in dcn_bw_sync_calcs_and_dml()
1732 dc->dml.ip.max_num_dpp = dc->dcn_ip->max_num_dpp; in dcn_bw_sync_calcs_and_dml()
1733 dc->dml.ip.max_num_wb = dc->dcn_ip->max_num_writeback; in dcn_bw_sync_calcs_and_dml()
1740 dc->dml.ip.max_hscl_taps = dc->dcn_ip->max_hscl_taps; in dcn_bw_sync_calcs_and_dml()
1741 dc->dml.ip.max_vscl_taps = dc->dcn_ip->max_vscl_taps; in dcn_bw_sync_calcs_and_dml()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn10/
A Ddcn10_fpu.c133 struct display_mode_lib *dml = &dc->dml; in dcn10_resource_construct_fp() local
135 dml->ip.max_num_dpp = 3; in dcn10_resource_construct_fp()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/
A Ddcn35_fpu.c321 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2; in dcn35_update_bw_bounding_box_fpu()
349 dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip, in dcn35_update_bw_bounding_box_fpu()
528 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 384;/*per guide*/ in dcn35_populate_dml_pipes_from_context_fpu()
542 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn35_populate_dml_pipes_from_context_fpu()
548 context->bw_ctx.dml.ip.det_buffer_size_kbytes = in dcn35_populate_dml_pipes_from_context_fpu()
551 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn35_populate_dml_pipes_from_context_fpu()
566 context->bw_ctx.dml.vba.ODMCombinePolicy = in dcn35_populate_dml_pipes_from_context_fpu()
597 bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency; in dcn35_decide_zstate_support()
600 bool allow_z10 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z10_residency; in dcn35_decide_zstate_support()
613 (int)context->bw_ctx.dml.vba.StutterPeriod); in dcn35_decide_zstate_support()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/
A Ddcn314_fpu.c265 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2; in dcn314_update_bw_bounding_box_fpu()
269 dml_init_instance(&dc->dml, &dcn3_14_soc, &dcn3_14_ip, DML_PROJECT_DCN314); in dcn314_update_bw_bounding_box_fpu()
392 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_14_DEFAULT_DET_SIZE; in dcn314_populate_dml_pipes_from_context_fpu()
402 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn314_populate_dml_pipes_from_context_fpu()
407 context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64; in dcn314_populate_dml_pipes_from_context_fpu()
409 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn314_populate_dml_pipes_from_context_fpu()
422 context->bw_ctx.dml.vba.ODMCombinePolicy = dm_odm_combine_policy_2to1; in dcn314_populate_dml_pipes_from_context_fpu()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn351/
A Ddcn351_fpu.c355 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2; in dcn351_update_bw_bounding_box_fpu()
383 dml_init_instance(&dc->dml, &dcn3_51_soc, &dcn3_51_ip, in dcn351_update_bw_bounding_box_fpu()
562 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 384;/*per guide*/ in dcn351_populate_dml_pipes_from_context_fpu()
576 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn351_populate_dml_pipes_from_context_fpu()
582 context->bw_ctx.dml.ip.det_buffer_size_kbytes = in dcn351_populate_dml_pipes_from_context_fpu()
585 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn351_populate_dml_pipes_from_context_fpu()
600 context->bw_ctx.dml.vba.ODMCombinePolicy = in dcn351_populate_dml_pipes_from_context_fpu()
631 bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency; in dcn351_decide_zstate_support()
/linux/drivers/gpu/drm/amd/display/dc/dml2/
A Ddml2_translation_helper.c568 const struct _vcs_dpi_ip_params_st *in_ip_params = &in->dml.ip; in dml2_translate_ip_params()
637 const struct _vcs_dpi_soc_bounding_box_st *in_soc_params = &in->dml.soc; in dml2_translate_socbb_params()
675 out->state_array[i].dcfclk_mhz = dc->dml.soc.clock_limits[i].dcfclk_mhz; in dml2_translate_soc_states()
676 out->state_array[i].dispclk_mhz = dc->dml.soc.clock_limits[i].dispclk_mhz; in dml2_translate_soc_states()
677 out->state_array[i].dppclk_mhz = dc->dml.soc.clock_limits[i].dppclk_mhz; in dml2_translate_soc_states()
679 out->state_array[i].dtbclk_mhz = dc->dml.soc.clock_limits[i].dtbclk_mhz; in dml2_translate_soc_states()
680 out->state_array[i].socclk_mhz = dc->dml.soc.clock_limits[i].socclk_mhz; in dml2_translate_soc_states()
682 out->state_array[i].dscclk_mhz = dc->dml.soc.clock_limits[i].dscclk_mhz; in dml2_translate_soc_states()
685 out->state_array[i].phyclk_mhz = dc->dml.soc.clock_limits[i].phyclk_mhz; in dml2_translate_soc_states()
687 out->state_array[i].sr_exit_time_us = dc->dml.soc.sr_exit_time_us; in dml2_translate_soc_states()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/
A DMakefile25 DC_LIBS = basics bios dml clk_mgr dce gpio hwss irq link virtual dsc resource optc dpp hubbub dccg …
38 DC_LIBS += dml
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/
A Ddcn30_resource.c1381 struct display_mode_lib *dml = &context->bw_ctx.dml; in dcn30_set_mcif_arb_params() local
1640 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn30_internal_validate_bw()
1646 context->bw_ctx.dml.vba.maxMpcComb = 0; in dcn30_internal_validate_bw()
1647 context->bw_ctx.dml.vba.VoltageLevel = 0; in dcn30_internal_validate_bw()
1669 if (vlevel < context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1687 if (vlevel < context->bw_ctx.dml.soc.num_states) { in dcn30_internal_validate_bw()
1692 context->bw_ctx.dml.validate_max_state = false; in dcn30_internal_validate_bw()
1695 dml_log_mode_support_params(&context->bw_ctx.dml); in dcn30_internal_validate_bw()
1697 if (vlevel == context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1870 context->bw_ctx.dml.vba.VoltageLevel = vlevel; in dcn30_internal_validate_bw()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/
A Ddcn21_resource.c801 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = in dcn21_fast_validate_bw()
803 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
805 if (vlevel > context->bw_ctx.dml.soc.num_states) { in dcn21_fast_validate_bw()
813 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = in dcn21_fast_validate_bw()
815 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
816 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn21_fast_validate_bw()
825 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn21_fast_validate_bw()
879 …dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe… in dcn21_fast_validate_bw()
883 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw()
905 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = in dcn21_fast_validate_bw()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn401/
A Ddcn401_fpu.c16 double pstate_latency_us = clk_mgr->ctx->dc->dml.soc.dram_clock_change_latency_us; in dcn401_build_wm_range_table_fpu()
17 double fclk_change_latency_us = clk_mgr->ctx->dc->dml.soc.fclk_change_latency_us; in dcn401_build_wm_range_table_fpu()
18 double sr_exit_time_us = clk_mgr->ctx->dc->dml.soc.sr_exit_time_us; in dcn401_build_wm_range_table_fpu()
19 double sr_enter_plus_exit_time_us = clk_mgr->ctx->dc->dml.soc.sr_enter_plus_exit_time_us; in dcn401_build_wm_range_table_fpu()
24 uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz; in dcn401_build_wm_range_table_fpu()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn302/
A Ddcn302_fpu.c218 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; in dcn302_fpu_update_bw_bounding_box()
343 dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); in dcn302_fpu_update_bw_bounding_box()
345 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); in dcn302_fpu_update_bw_bounding_box()
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/
A Ddml2_internal_shared_types.h889 struct dml2_instance *dml; member
895 struct dml2_instance *dml; member
902 struct dml2_instance *dml; member
908 struct dml2_instance *dml; member
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn303/
A Ddcn303_fpu.c214 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; in dcn303_fpu_update_bw_bounding_box()
362 dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30); in dcn303_fpu_update_bw_bounding_box()
364 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30); in dcn303_fpu_update_bw_bounding_box()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/
A Ddcn20_resource.c1855 struct vba_vars_st *v = &context->bw_ctx.dml.vba; in dcn20_validate_apply_pipe_split_flags()
1910 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) in dcn20_validate_apply_pipe_split_flags()
1915 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_validate_apply_pipe_split_flags()
2063 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn20_fast_validate_bw()
2065 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_fast_validate_bw()
2083 …if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn20_fast_validate_bw()
2102 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) in dcn20_fast_validate_bw()
2112 …dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe… in dcn20_fast_validate_bw()
2116 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn20_fast_validate_bw()
2138 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = in dcn20_fast_validate_bw()
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