| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | display_mode_vba_util_32.c | 222 dml_ceil((double) HTaps / 6.0, 1.0)); in dml32_CalculateSinglePipeDPPCLKAndSCLThroughput()
803 dml_ceil(SwathWidthY[k] - 1, in dml32_CalculateSwathWidth()
818 dml_ceil(SwathWidthC[k] - 1, in dml32_CalculateSwathWidth()
1704 HCActive = dml_ceil(DSCSlices * dml_ceil(OutputBpp * in dml32_RequiredDTBCLK()
1841 dml_min(dml_ceil(DCCMetaPitchC[k], 8 * in dml32_CalculateSurfaceSizeInMall()
1848 dml_min(dml_ceil(SurfaceHeightC[k], 8 * in dml32_CalculateSurfaceSizeInMall()
2908 dml_ceil(((double)WritebackSourceHeight - in dml32_CalculateWriteBackDelay()
5194 num_group_per_lower_vm_stage = dml_ceil( in dml32_CalculateVMGroupAndRequestTimes()
5200 num_group_per_lower_vm_stage = dml_ceil( in dml32_CalculateVMGroupAndRequestTimes()
5207 num_group_per_lower_vm_stage = dml_ceil( in dml32_CalculateVMGroupAndRequestTimes()
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| A D | display_rq_dlg_calc_32.c | 294 …dst_x_after_scaler = dml_ceil(get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx… in dml32_rq_dlg_get_dlg_reg()
295 …dst_y_after_scaler = dml_ceil(get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx… in dml32_rq_dlg_get_dlg_reg()
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| A D | display_mode_vba_32.c | 700 dml_ceil((double) v->WritebackDelay[mode_lib->vba.VoltageLevel][k] in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1446 dml_ceil(v->WritebackDelay[mode_lib->vba.VoltageLevel][k] in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1833 v->ReadBandwidthLuma[k] = v->SwathWidthYSingleDPP[k] * dml_ceil(v->BytePerPixelInDETY[k], 1.0) in dml32_ModeSupportAndSystemConfigurationFull()
1835 …v->ReadBandwidthChroma[k] = v->SwathWidthYSingleDPP[k] / 2 * dml_ceil(v->BytePerPixelInDETC[k], 2.… in dml32_ModeSupportAndSystemConfigurationFull()
1940 / (mode_lib->vba.vtaps[k] + dml_max(dml_ceil(mode_lib->vba.VRatio[k], 1.0) - 2, 0.0)); in dml32_ModeSupportAndSystemConfigurationFull()
1947 + dml_max(dml_ceil(mode_lib->vba.VRatioChroma[k], 1.0) - 2, in dml32_ModeSupportAndSystemConfigurationFull()
2967 - dml_max(1.0, dml_ceil(1.0 * in dml32_ModeSupportAndSystemConfigurationFull()
3631 mode_lib->vba.AlignedYPitch[k] = dml_ceil( in dml32_ModeSupportAndSystemConfigurationFull()
3635 mode_lib->vba.AlignedDCCMetaPitchY[k] = dml_ceil( in dml32_ModeSupportAndSystemConfigurationFull()
3646 mode_lib->vba.AlignedCPitch[k] = dml_ceil( in dml32_ModeSupportAndSystemConfigurationFull()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| A D | display_mode_vba_21.c | 1325 * (dml_ceil( in CalculateVMAndRowBytes()
1507 / dml_ceil( in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1672 * dml_ceil( in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1806 dml_ceil( in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1887 dml_ceil( in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2119 dml_ceil( in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2646 dml_ceil( in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2652 dml_ceil( in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3079 * dml_ceil( in CalculateWriteBackDelay()
3094 dml_ceil( in CalculateWriteBackDelay()
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| A D | display_rq_dlg_calc_21.c | 448 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); in get_meta_and_pte_attr()
684 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil( in get_meta_and_pte_attr()
1737 cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) in calculate_ttu_cursor()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | display_mode_vba_20.c | 919 * (dml_ceil( in CalculateVMAndRowBytes()
1054 * (dml_ceil( in CalculateVMAndRowBytes()
1066 * (dml_ceil( in CalculateVMAndRowBytes()
1123 / dml_ceil( in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1292 * dml_ceil( in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1814 dml_ceil( in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1916 dml_ceil( in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2030 dml_ceil( in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2070 dml_ceil( in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2640 dml_ceil( in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
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| A D | display_mode_vba_20v2.c | 979 * (dml_ceil( in CalculateVMAndRowBytes()
1114 * (dml_ceil( in CalculateVMAndRowBytes()
1126 * (dml_ceil( in CalculateVMAndRowBytes()
1183 / dml_ceil( in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1352 * dml_ceil( in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1850 dml_ceil( in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1952 dml_ceil( in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2066 dml_ceil( in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2106 dml_ceil( in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2713 dml_ceil( in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
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| A D | display_rq_dlg_calc_20.c | 456 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); in get_meta_and_pte_attr()
677 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width, in get_meta_and_pte_attr()
1623 cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) in calculate_ttu_cursor()
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| A D | display_rq_dlg_calc_20v2.c | 456 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); in get_meta_and_pte_attr()
677 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width, in get_meta_and_pte_attr()
1624 cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) in calculate_ttu_cursor()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| A D | display_mode_vba_30.c | 1025 Tvm_oto_lines = dml_ceil(4.0 * Tvm_oto / LineTime, 1) / 4.0; in CalculatePrefetchSchedule()
1026 Tr0_oto_lines = dml_ceil(4.0 * Tr0_oto / LineTime, 1) / 4.0; in CalculatePrefetchSchedule()
1305 return VCOSpeed * 4 / dml_ceil(VCOSpeed * 4.0 / Clock, 1); in RoundToDFSGranularityDown()
1645 *MaxNumSwath = dml_ceil(*VInitPreFill / SwathHeight, 1); in CalculatePrefetchSourceLines()
2019 * dml_ceil( in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2139 dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2147 dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2155 dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2519 v->VUpdateOffsetPix[k] = dml_ceil(v->HTotal[k] / 4.0, 1); in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2526 v->VUpdateOffsetPix[k] = dml_ceil(v->HTotal[x] / 4.0, 1); in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
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| A D | display_rq_dlg_calc_30.c | 405 + dml_ceil((double)(log2_blk_bytes - 8) / 2.0, 1); in get_meta_and_pte_attr()
651 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double)dpte_row_width_ub / dpte_group_width, in get_meta_and_pte_attr()
839 cur_width_ub = dml_ceil((double)cur_src_width / (double)cur_req_width, 1) in calculate_ttu_cursor()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | display_mode_vba_31.c | 1104 Tvm_oto_lines = dml_ceil(4.0 * Tvm_oto / LineTime, 1) / 4.0;
1105 Tr0_oto_lines = dml_ceil(4.0 * Tr0_oto / LineTime, 1) / 4.0;
1469 return VCOSpeed * 4 / dml_ceil(VCOSpeed * 4.0 / Clock, 1);
1769 *MaxNumSwath = dml_ceil(*VInitPreFill / SwathHeight, 1);
1887 * (dml_ceil(
1893 * (dml_ceil(
2261 dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
2549 dml_ceil(
3429 *VUpdateOffsetPix = dml_ceil(HTotal / 4.0, 1);
5009 dml_ceil(
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| A D | display_rq_dlg_calc_31.c | 425 log2_blk_height = log2_blk256_height + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); in get_meta_and_pte_attr()
646 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width, 1); in get_meta_and_pte_attr()
820 …cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) * (double) cur_req_wid… in calculate_ttu_cursor()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| A D | display_mode_vba_314.c | 1122 Tvm_oto_lines = dml_ceil(4.0 * Tvm_oto / LineTime, 1) / 4.0;
1123 Tr0_oto_lines = dml_ceil(4.0 * Tr0_oto / LineTime, 1) / 4.0;
1486 return VCOSpeed * 4 / dml_ceil(VCOSpeed * 4.0 / Clock, 1);
1786 *MaxNumSwath = dml_ceil(*VInitPreFill / SwathHeight, 1);
1904 * (dml_ceil(
1910 * (dml_ceil(
2279 dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
3535 *VUpdateOffsetPix = dml_ceil(HTotal / 4.0, 1);
4100 / (v->vtaps[k] + dml_max(dml_ceil(v->VRatio[k], 1.0) - 2, 0.0));
4687 dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0),
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| A D | dcn314_fpu.c | 291 num_lines = dml_ceil(1000.0 * num_us / lines_time_in_ns, 1.0); in micro_sec_to_vert_lines()
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| A D | display_rq_dlg_calc_314.c | 513 log2_blk_height = log2_blk256_height + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); in get_meta_and_pte_attr()
734 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width, 1); in get_meta_and_pte_attr()
907 …cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) * (double) cur_req_wid… in calculate_ttu_cursor()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| A D | display_mode_vba.c | 1131 dml_ceil(WritebackLumaHTaps / 4.0, 1) / WritebackHRatio, in CalculateWriteBackDISPCLK()
1132 …dml_max((WritebackLumaVTaps * dml_ceil(1.0 / WritebackVRatio, 1) * dml_ceil(WritebackDestinationWi… in CalculateWriteBackDISPCLK()
1133 …+ dml_ceil(WritebackDestinationWidth / 4.0, 1)) / (double) HTotal + dml_ceil(1.0 / WritebackVRatio… in CalculateWriteBackDISPCLK()
1134 * (dml_ceil(WritebackLumaVTaps / 4.0, 1) + 4.0) / (double) HTotal, in CalculateWriteBackDISPCLK()
1135 dml_ceil(1.0 / WritebackVRatio, 1) * WritebackDestinationWidth / (double) HTotal)); in CalculateWriteBackDISPCLK()
1138 dml_ceil(WritebackChromaHTaps / 2.0, 1) / (2 * WritebackHRatio), in CalculateWriteBackDISPCLK()
1139 …dml_max((WritebackChromaVTaps * dml_ceil(1 / (2 * WritebackVRatio), 1) * dml_ceil(WritebackDestina… in CalculateWriteBackDISPCLK()
1140 + dml_ceil(WritebackDestinationWidth / 2.0 / WritebackChromaLineBufferWidth, 1)) / HTotal in CalculateWriteBackDISPCLK()
1141 … + dml_ceil(1 / (2 * WritebackVRatio), 1) * (dml_ceil(WritebackChromaVTaps / 4.0, 1) + 4) / HTotal, in CalculateWriteBackDISPCLK()
1142 dml_ceil(1.0 / (2 * WritebackVRatio), 1) * WritebackDestinationWidth / 2.0 / HTotal))); in CalculateWriteBackDISPCLK()
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| A D | dml_inline_defs.h | 67 static inline double dml_ceil(double a, double granularity) in dml_ceil() function
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| A D | dml1_display_rq_dlg_calc.c | 185 …*max_num_sw = (unsigned int) (dml_ceil((prefill - 1.0) / (double) swath_height, 1) + 1.0); /* pref… in get_swath_need()
447 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); in dml1_rq_dlg_get_row_heights()
687 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); in get_surf_rq_param()
923 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil( in get_surf_rq_param()
1846 cur0_width_ub = dml_ceil((double) cur0_src_width / (double) cur0_req_width, 1) in dml1_rq_dlg_get_dlg_params()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | display_mode_core.c | 1220 s->Tvm_oto_lines = dml_ceil(4.0 * s->Tvm_oto / s->LineTime, 1) / 4.0; in CalculatePrefetchSchedule()
1221 s->Tr0_oto_lines = dml_ceil(4.0 * s->Tr0_oto / s->LineTime, 1) / 4.0; in CalculatePrefetchSchedule()
1815 DISPCLK_H = PixelClock * dml_ceil(WritebackHTaps / 8.0, 1) / WritebackHRatio; in CalculateWriteBackDISPCLK()
1873 *VUpdateOffsetPix = (dml_uint_t)(dml_ceil(HTotal / 4.0, 1.0)); in CalculateVUpdateAndDynamicMetadataParameters()
2090 return VCOSpeed * 4.0 / dml_ceil(VCOSpeed * 4.0 / Clock, 1.0); in RoundToDFSGranularity()
2788 *RequiredSlots = (dml_uint_t)(dml_ceil(DesiredBPP / MaxLinkBPP * 64, 1)); in TruncToValidBPP()
4398 surface_width_ub_l = (dml_uint_t)dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]); in CalculateSwathWidth()
4588 …dml_float_t HCActive = dml_ceil(DSCSlices * dml_ceil(OutputBpp * dml_ceil(HActive / DSCSlices, 1) … in RequiredDTBCLK()
5708 Dppclk[k] = *GlobalDPPCLK / 255.0 * dml_ceil(Dppclk[k] * 255.0 / *GlobalDPPCLK, 1.0); in CalculateDPPCLK()
6164 return dml_ceil(1000.0 * num_us / lines_time_in_ns, 1.0); in MicroSecToVertLines()
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| A D | display_mode_util.h | 38 __DML_DLL_EXPORT__ dml_float_t dml_ceil(dml_float_t x, dml_float_t granularity);
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| A D | display_mode_util.c | 108 dml_float_t dml_ceil(dml_float_t x, dml_float_t granularity) in dml_ceil() function
186 double ceil = dml_ceil(val, 1); in dml_round()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
| A D | dcn35_fpu.c | 419 num_lines = dml_ceil(1000.0 * num_us / lines_time_in_ns, 1.0); in micro_sec_to_vert_lines()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn351/ |
| A D | dcn351_fpu.c | 453 num_lines = dml_ceil(1000.0 * num_us / lines_time_in_ns, 1.0); in micro_sec_to_vert_lines()
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