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Searched refs:dml_core_ctx (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml2/
A Ddml2_wrapper.c74 if (dml2->v20.dml_core_ctx.project != dml_project_dcn35 && in map_hw_resources()
75 dml2->v20.dml_core_ctx.project != dml_project_dcn351) { in map_hw_resources()
100 s->mode_support_params.mode_lib = &dml2->v20.dml_core_ctx; in pack_and_call_dml_mode_support_ex()
237 build_unoptimized_policy_settings(dml2->v20.dml_core_ctx.project, &dml2->v20.dml_core_ctx.policy); in calculate_lowest_supported_state_for_temp_read()
342 build_unoptimized_policy_settings(dml2->v20.dml_core_ctx.project, &dml2->v20.dml_core_ctx.policy); in dml_mode_support_wrapper()
379 s->cur_policy = dml2->v20.dml_core_ctx.policy; in dml_mode_support_wrapper()
380 s->optimize_configuration_params.dml_core_ctx = &dml2->v20.dml_core_ctx; in dml_mode_support_wrapper()
390 dml2->v20.dml_core_ctx.policy = s->new_policy; in dml_mode_support_wrapper()
404 dml2->v20.dml_core_ctx.policy = s->cur_policy; in dml_mode_support_wrapper()
687 build_unoptimized_policy_settings(dml2->v20.dml_core_ctx.project, &dml2->v20.dml_core_ctx.policy); in dml2_validate_only()
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A Ddml2_utils.c339 dml_rq_dlg_get_rq_reg(&s->rq_regs, &in_ctx->v20.dml_core_ctx, dml_pipe_idx); in dml2_calculate_rq_and_dlg_params()
377 watermark->urgent_ns = dml_get_wm_urgent(dml_core_ctx) * 1000; in dml2_extract_watermark_set()
379 watermark->cstate_pstate.cstate_exit_ns = dml_get_wm_stutter_exit(dml_core_ctx) * 1000; in dml2_extract_watermark_set()
381 watermark->pte_meta_urgent_ns = dml_get_wm_memory_trip(dml_core_ctx) * 1000; in dml2_extract_watermark_set()
382 watermark->frac_urg_bw_nom = dml_get_fraction_of_urgent_bandwidth(dml_core_ctx) * 1000; in dml2_extract_watermark_set()
384 watermark->urgent_latency_ns = dml_get_urgent_latency(dml_core_ctx) * 1000; in dml2_extract_watermark_set()
386 watermark->usr_retraining_ns = dml_get_wm_usr_retraining(dml_core_ctx) * 1000; in dml2_extract_watermark_set()
388 watermark->cstate_pstate.cstate_exit_z8_ns = dml_get_wm_z8_stutter(dml_core_ctx) * 1000; in dml2_extract_watermark_set()
436 dml_get_wm_writeback_urgent(dml_core_ctx) * 1000; in dml2_extract_writeback_wm()
438 dml_get_wm_writeback_dram_clock_change(dml_core_ctx) * 1000; in dml2_extract_writeback_wm()
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A Ddml2_utils.h42 …_extract_watermark_set(struct dcn_watermarks *watermark, struct display_mode_lib_st *dml_core_ctx);
43 void dml2_extract_writeback_wm(struct dc_state *context, struct display_mode_lib_st *dml_core_ctx);
A Ddml2_translation_helper.c36 switch (dml2->v20.dml_core_ctx.project) { in dml2_init_ip_params()
278 switch (dml2->v20.dml_core_ctx.project) { in dml2_init_socbb_params()
332 unsigned int dml_project = dml2->v20.dml_core_ctx.project; in dml2_init_soc_states()
351 switch (dml2->v20.dml_core_ctx.project) { in dml2_init_soc_states()
501 if ((dml2->v20.dml_core_ctx.project == dml_project_dcn32) || in dml2_init_soc_states()
502 (dml2->v20.dml_core_ctx.project == dml_project_dcn321)) { in dml2_init_soc_states()
509 dml2->v20.dml_core_ctx.project != dml_project_dcn351) { in dml2_init_soc_states()
557 if (dml2->v20.dml_core_ctx.project == dml_project_dcn35) { in dml2_init_soc_states()
1284 if (dml2->v20.dml_core_ctx.ip.hostvm_enable) in map_dc_state_into_dml_display_cfg()
1333 context->streams[i], &dml2->v20.dml_core_ctx.soc); in map_dc_state_into_dml_display_cfg()
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A Ddml2_internal_types.h39 struct display_mode_lib_st *dml_core_ctx; member
142 struct display_mode_lib_st dml_core_ctx; member
A Ddml2_mall_phantom.c904 vstartup = dml_get_vstartup_calculated(&ctx->v20.dml_core_ctx, dml_pipe_idx); in dml2_svp_add_phantom_pipe_to_dc_state()

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