| /linux/drivers/gpu/drm/i915/display/ |
| A D | intel_dp_link_training.c | 67 enum drm_dp_phy dp_phy) in intel_dp_lttpr_phy_caps() argument
74 enum drm_dp_phy dp_phy) in intel_dp_read_lttpr_phy_caps() argument
499 lt_dbg(intel_dp, dp_phy, in intel_dp_get_adjust_train()
505 lt_dbg(intel_dp, dp_phy, in intel_dp_get_adjust_train()
531 enum drm_dp_phy dp_phy, in intel_dp_set_link_train() argument
606 enum drm_dp_phy dp_phy) in intel_dp_set_signal_levels() argument
611 lt_dbg(intel_dp, dp_phy, in intel_dp_set_signal_levels()
617 lt_dbg(intel_dp, dp_phy, in intel_dp_set_signal_levels()
849 lt_dbg(intel_dp, dp_phy, in intel_dp_dump_link_status()
1140 enum drm_dp_phy dp_phy) in intel_dp_link_train_phy() argument
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| A D | intel_dp_link_training.h | 27 enum drm_dp_phy dp_phy,
31 enum drm_dp_phy dp_phy,
35 enum drm_dp_phy dp_phy);
43 intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy,
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| /linux/drivers/phy/mediatek/ |
| A D | phy-mtk-dp.c | 87 struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy); in mtk_dp_phy_init() local
111 struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy); in mtk_dp_phy_configure() local
134 regmap_write(dp_phy->regs, MTK_DP_PHY_DIG_BIT_RATE, val); in mtk_dp_phy_configure()
145 struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy); in mtk_dp_phy_reset() local
147 regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_SW_RST, in mtk_dp_phy_reset()
150 regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_SW_RST, in mtk_dp_phy_reset()
166 struct mtk_dp_phy *dp_phy; in mtk_dp_phy_probe() local
175 dp_phy = devm_kzalloc(dev, sizeof(*dp_phy), GFP_KERNEL); in mtk_dp_phy_probe()
176 if (!dp_phy) in mtk_dp_phy_probe()
179 dp_phy->regs = regs; in mtk_dp_phy_probe()
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| /linux/include/drm/display/ |
| A D | drm_dp.h | 1501 #define DP_LTTPR_BASE(dp_phy) \ argument
1503 ((dp_phy) - DP_PHY_LTTPR1))
1505 #define DP_LTTPR_REG(dp_phy, lttpr1_reg) \ argument
1533 #define DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy) \ argument
1547 #define DP_OUI_PHY_REPEATER(dp_phy) \ argument
1548 DP_LTTPR_REG(dp_phy, DP_OUI_PHY_REPEATER1)
1552 #define DP_FEC_BASE(dp_phy) \ argument
1554 ((dp_phy) - DP_PHY_LTTPR1)))
1556 #define DP_FEC_REG(dp_phy, fec1_reg) \ argument
1560 #define DP_FEC_STATUS_PHY_REPEATER(dp_phy) \ argument
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| A D | drm_dp_helper.h | 48 enum drm_dp_phy dp_phy, bool uhbr);
50 enum drm_dp_phy dp_phy, bool uhbr);
72 const char *drm_dp_phy_name(enum drm_dp_phy dp_phy);
567 enum drm_dp_phy dp_phy,
624 enum drm_dp_phy dp_phy,
661 int drm_dp_dump_lttpr_desc(struct drm_dp_aux *aux, enum drm_dp_phy dp_phy);
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| /linux/drivers/gpu/drm/display/ |
| A D | drm_dp_helper.c | 286 enum drm_dp_phy dp_phy, bool uhbr, bool cr) in __read_delay() argument
292 if (dp_phy == DP_PHY_DPRX) { in __read_delay()
341 enum drm_dp_phy dp_phy, bool uhbr) in drm_dp_read_clock_recovery_delay() argument
348 enum drm_dp_phy dp_phy, bool uhbr) in drm_dp_read_channel_eq_delay() argument
431 if (dp_phy < 0 || dp_phy >= ARRAY_SIZE(phy_names) || in drm_dp_phy_name()
432 WARN_ON(!phy_names[dp_phy])) in drm_dp_phy_name()
435 return phy_names[dp_phy]; in drm_dp_phy_name()
743 enum drm_dp_phy dp_phy, in drm_dp_dpcd_read_phy_link_status() argument
748 if (dp_phy == DP_PHY_DPRX) { in drm_dp_dpcd_read_phy_link_status()
2401 if (drm_WARN_ON(aux->drm_dev, dp_phy < DP_PHY_LTTPR1 || dp_phy > DP_MAX_LTTPR_COUNT)) in drm_dp_dump_lttpr_desc()
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| /linux/Documentation/devicetree/bindings/clock/ |
| A D | qcom,dispcc-sm6350.yaml | 62 <&dp_phy 0>,
63 <&dp_phy 1>;
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| A D | qcom,sc7180-dispcc.yaml | 62 <&dp_phy 0>,
63 <&dp_phy 1>;
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| A D | qcom,sc7280-dispcc.yaml | 66 <&dp_phy 0>,
67 <&dp_phy 1>,
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| A D | qcom,sm7150-dispcc.yaml | 68 <&dp_phy 0>,
69 <&dp_phy 1>;
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| A D | qcom,sdm845-dispcc.yaml | 74 <&dp_phy 0>,
75 <&dp_phy 1>;
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| A D | qcom,dispcc-sm6125.yaml | 87 <&dp_phy 0>,
88 <&dp_phy 1>,
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| A D | qcom,dispcc-sm8x50.yaml | 108 <&dp_phy 0>,
109 <&dp_phy 1>;
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| /linux/Documentation/devicetree/bindings/display/msm/ |
| A D | dp-controller.yaml | 206 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
208 phys = <&dp_phy>;
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| A D | qcom,sc7180-mdss.yaml | 272 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
273 phys = <&dp_phy>;
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| A D | qcom,sc7280-mdss.yaml | 392 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
393 phys = <&dp_phy>;
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| A D | qcom,sm7150-mdss.yaml | 404 assigned-clock-parents = <&dp_phy 0>,
405 <&dp_phy 1>;
410 phys = <&dp_phy>;
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| /linux/Documentation/devicetree/bindings/display/rockchip/ |
| A D | rockchip,analogix-dp.yaml | 68 phys = <&dp_phy>;
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| /linux/Documentation/devicetree/bindings/display/bridge/ |
| A D | cdns,mhdp8546.yaml | 140 phys = <&dp_phy>;
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| /linux/Documentation/devicetree/bindings/display/samsung/ |
| A D | samsung,exynos5-dp.yaml | 144 phys = <&dp_phy>;
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| /linux/drivers/phy/qualcomm/ |
| A D | phy-qcom-qmp-combo.c | 1642 struct phy *dp_phy; member
3657 return qmp->dp_phy; in qmp_combo_phy_xlate()
3744 qmp->dp_phy = devm_phy_create(dev, dp_np, &qmp_combo_dp_phy_ops); in qmp_combo_probe()
3745 if (IS_ERR(qmp->dp_phy)) { in qmp_combo_probe()
3746 ret = PTR_ERR(qmp->dp_phy); in qmp_combo_probe()
3751 phy_set_drvdata(qmp->dp_phy, qmp); in qmp_combo_probe()
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| /linux/arch/arm/boot/dts/samsung/ |
| A D | exynos5250.dtsi | 298 dp_phy: dp-phy { label
1126 phys = <&dp_phy>;
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| A D | exynos5420.dtsi | 933 dp_phy: dp-phy { label
1213 phys = <&dp_phy>;
|