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Searched refs:dpcd (Results 1 – 25 of 52) sorted by relevance

123

/linux/include/drm/display/
A Ddrm_dp_helper.h56 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
154 return dpcd[DP_DPCD_REV] >= 0x11 && in drm_dp_enhanced_frame_cap()
161 return dpcd[DP_DPCD_REV] >= 0x11 && in drm_dp_fast_training_cap()
168 return dpcd[DP_DPCD_REV] >= 0x12 && in drm_dp_tps3_supported()
175 return dpcd[DP_DPCD_REV] >= 0x11 || in drm_dp_max_downspread()
182 return dpcd[DP_DPCD_REV] >= 0x14 && in drm_dp_tps4_supported()
265 return dpcd[DP_EDP_CONFIGURATION_CAP] & in drm_dp_alternate_scrambler_reset_cap()
273 return dpcd[DP_DOWN_STREAM_PORT_COUNT] & in drm_dp_sink_can_do_video_without_timing_msa()
561 u8 dpcd[DP_RECEIVER_CAP_SIZE]);
574 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
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/linux/drivers/gpu/drm/display/
A Ddrm_dp_helper.c327 rd_interval = dpcd[offset]; in __read_delay()
1017 if (!drm_dp_is_branch(dpcd) || dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) in drm_dp_read_downstream_info()
1054 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_max_dotclock()
1084 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_max_tmds_clock()
1149 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_min_tmds_clock()
1192 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_max_bpc()
1247 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_420_passthrough()
1278 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_444_to_420_conversion()
1310 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_rgb_to_ycbcr_conversion()
1346 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_mode()
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/linux/drivers/gpu/drm/nouveau/
A Dnouveau_dp.c69 u8 *dpcd = outp->dp.dpcd; in nouveau_dp_probe_dpcd() local
78 !drm_dp_read_dpcd_caps(aux, dpcd) && in nouveau_dp_probe_dpcd()
99 ret = drm_dp_read_dpcd_caps(aux, dpcd); in nouveau_dp_probe_dpcd()
134 outp->dp.rate[j].dpcd = i; in nouveau_dp_probe_dpcd()
143 u32 max_rate = dpcd[DP_MAX_LINK_RATE] * 27000; in nouveau_dp_probe_dpcd()
156 outp->dp.rate[outp->dp.rate_nr].dpcd = -1; in nouveau_dp_probe_dpcd()
202 ret = drm_dp_read_downstream_info(aux, dpcd, in nouveau_dp_probe_dpcd()
225 u8 *dpcd = nv_encoder->dp.dpcd; in nouveau_dp_detect() local
340 if ( (outp->dp.dpcd[DP_MAX_LANE_COUNT] & 0x20) && in nouveau_dp_train_link()
341 !(outp->dp.dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED)) in nouveau_dp_train_link()
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/linux/drivers/gpu/drm/bridge/analogix/
A Danalogix-anx6345.c63 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
99 u8 dp_bw, dpcd[2]; in anx6345_dp_link_training() local
150 if (anx6345->dpcd[DP_DPCD_REV] >= 0x11) { in anx6345_dp_link_training()
158 dpcd[0] &= ~DP_SET_POWER_MASK; in anx6345_dp_link_training()
159 dpcd[0] |= DP_SET_POWER_D0; in anx6345_dp_link_training()
212 dpcd[0] = dp_bw; in anx6345_dp_link_training()
214 SP_DP_MAIN_LINK_BW_SET_REG, dpcd[0]); in anx6345_dp_link_training()
218 dpcd[1] = drm_dp_max_lane_count(anx6345->dpcd); in anx6345_dp_link_training()
221 SP_DP_LANE_COUNT_SET_REG, dpcd[1]); in anx6345_dp_link_training()
226 dpcd[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; in anx6345_dp_link_training()
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A Danalogix-anx78xx.c83 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
606 u8 dp_bw, dpcd[2]; in anx78xx_dp_link_training() local
663 if (anx78xx->dpcd[DP_DPCD_REV] >= 0x11) { in anx78xx_dp_link_training()
671 dpcd[0] &= ~DP_SET_POWER_MASK; in anx78xx_dp_link_training()
672 dpcd[0] |= DP_SET_POWER_D0; in anx78xx_dp_link_training()
714 if (drm_dp_enhanced_frame_cap(anx78xx->dpcd)) in anx78xx_dp_link_training()
727 anx78xx->dpcd[DP_MAX_LINK_RATE]); in anx78xx_dp_link_training()
731 dpcd[1] = drm_dp_max_lane_count(anx78xx->dpcd); in anx78xx_dp_link_training()
733 if (drm_dp_enhanced_frame_cap(anx78xx->dpcd)) in anx78xx_dp_link_training()
734 dpcd[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; in anx78xx_dp_link_training()
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/linux/drivers/gpu/drm/amd/amdgpu/
A Datombios_dp.c253 const u8 dpcd[DP_DPCD_SIZE], in amdgpu_atombios_dp_get_dp_link_config()
260 unsigned max_link_rate = drm_dp_max_link_rate(dpcd); in amdgpu_atombios_dp_get_dp_link_config()
339 if (dig_connector->dpcd[DP_DPCD_REV] > 0x10) { in amdgpu_atombios_dp_ds_ports()
359 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); in amdgpu_atombios_dp_get_dpcd()
362 dig_connector->dpcd); in amdgpu_atombios_dp_get_dpcd()
369 dig_connector->dpcd[0] = 0; in amdgpu_atombios_dp_get_dpcd()
481 if (dig_connector->dpcd[0] >= 0x11) { in amdgpu_atombios_dp_set_rx_power_state()
495 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
549 if (dp_info->dpcd[3] & 0x1) in amdgpu_atombios_dp_link_train_init()
561 if (drm_dp_enhanced_frame_cap(dp_info->dpcd)) in amdgpu_atombios_dp_link_train_init()
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/linux/drivers/gpu/drm/radeon/
A Datombios_dp.c302 const u8 dpcd[DP_DPCD_SIZE], in radeon_dp_get_dp_link_config()
308 unsigned max_link_rate = drm_dp_max_link_rate(dpcd); in radeon_dp_get_dp_link_config()
309 unsigned max_lane_num = drm_dp_max_lane_count(dpcd); in radeon_dp_get_dp_link_config()
391 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); in radeon_dp_getdpcd()
394 dig_connector->dpcd); in radeon_dp_getdpcd()
401 dig_connector->dpcd[0] = 0; in radeon_dp_getdpcd()
524 if (dig_connector->dpcd[0] >= 0x11) { in radeon_dp_set_rx_power_state()
540 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
605 if (dp_info->dpcd[3] & 0x1) in radeon_dp_link_train_init()
617 if (drm_dp_enhanced_frame_cap(dp_info->dpcd)) in radeon_dp_link_train_init()
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/linux/drivers/gpu/drm/msm/dp/
A Ddp_panel.c35 if (dp_panel->dpcd[DP_EDP_CONFIGURATION_CAP]) { in dp_panel_read_psr_cap()
53 u8 *dpcd, major, minor; in dp_panel_read_dpcd() local
56 dpcd = dp_panel->dpcd; in dp_panel_read_dpcd()
57 rc = drm_dp_read_dpcd_caps(panel->aux, dpcd); in dp_panel_read_dpcd()
61 dp_panel->vsc_sdp_supported = drm_dp_vsc_sdp_supported(panel->aux, dpcd); in dp_panel_read_dpcd()
63 link_info->revision = dpcd[DP_DPCD_REV]; in dp_panel_read_dpcd()
67 link_info->rate = drm_dp_max_link_rate(dpcd); in dp_panel_read_dpcd()
68 link_info->num_lanes = drm_dp_max_lane_count(dpcd); in dp_panel_read_dpcd()
82 if (drm_dp_enhanced_frame_cap(dpcd)) in dp_panel_read_dpcd()
143 if (drm_dp_is_branch(dp_panel->dpcd)) { in dp_panel_read_sink_caps()
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A Ddp_ctrl.c140 const u8 *dpcd = ctrl->panel->dpcd; in dp_ctrl_config_ctrl() local
149 if (drm_dp_alternate_scrambler_reset_cap(dpcd)) in dp_ctrl_config_ctrl()
161 if (drm_dp_enhanced_frame_cap(dpcd)) in dp_ctrl_config_ctrl()
1219 drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd); in dp_ctrl_clear_training_pattern()
1235 if (drm_dp_tps4_supported(ctrl->panel->dpcd)) { in dp_ctrl_link_train_2()
1238 } else if (drm_dp_tps3_supported(ctrl->panel->dpcd)) { in dp_ctrl_link_train_2()
1278 const u8 *dpcd = ctrl->panel->dpcd; in dp_ctrl_link_train() local
1293 if (drm_dp_max_downspread(dpcd)) in dp_ctrl_link_train()
1299 if (drm_dp_alternate_scrambler_reset_cap(dpcd)) { in dp_ctrl_link_train()
1448 const u8 *dpcd = ctrl->panel->dpcd; in dp_ctrl_enable_mainlink_clocks() local
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/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
A Ddp.c242 if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] >= 0x14 && in nvkm_dp_train_eq()
243 lt->outp->dp.dpcd[DPCD_RC03] & DPCD_RC03_TPS4_SUPPORTED) in nvkm_dp_train_eq()
246 if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] >= 0x12 && in nvkm_dp_train_eq()
247 lt->outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED) in nvkm_dp_train_eq()
318 .pc2 = outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED, in nvkm_dp_train_link()
327 sink[0] = (outp->dp.rate[rate].dpcd < 0) ? ior->dp.bw : 0; in nvkm_dp_train_link()
338 if (outp->dp.rate[rate].dpcd >= 0) { in nvkm_dp_train_link()
344 sink[0] |= outp->dp.rate[rate].dpcd; in nvkm_dp_train_link()
382 outp->dp.dpcd[DPCD_RC03] &= ~DPCD_RC03_TPS4_SUPPORTED; in nvkm_dp_train_links()
384 outp->dp.dpcd[DPCD_RC02] &= ~DPCD_RC02_TPS3_SUPPORTED; in nvkm_dp_train_links()
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A Doutp.h48 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
51 int dpcd; /* -1, or index into SUPPORTED_LINK_RATES table */ member
A Duoutp.c90 outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP, in nvkm_uoutp_mthd_dp_sst()
118 memcpy(outp->dp.dpcd, args->v0.dpcd, sizeof(outp->dp.dpcd)); in nvkm_uoutp_mthd_dp_train()
140 outp->dp.rate[i].dpcd = args->v0.rate[i].dpcd; in nvkm_uoutp_mthd_dp_rates()
/linux/drivers/gpu/drm/tegra/
A Ddp.c172 u8 dpcd[DP_RECEIVER_CAP_SIZE], value; in drm_dp_link_probe() local
178 err = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, sizeof(dpcd)); in drm_dp_link_probe()
182 link->revision = dpcd[DP_DPCD_REV]; in drm_dp_link_probe()
183 link->max_rate = drm_dp_max_link_rate(dpcd); in drm_dp_link_probe()
184 link->max_lanes = drm_dp_max_lane_count(dpcd); in drm_dp_link_probe()
186 link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(dpcd); in drm_dp_link_probe()
187 link->caps.tps3_supported = drm_dp_tps3_supported(dpcd); in drm_dp_link_probe()
188 link->caps.fast_training = drm_dp_fast_training_cap(dpcd); in drm_dp_link_probe()
189 link->caps.channel_coding = drm_dp_channel_coding_supported(dpcd); in drm_dp_link_probe()
191 if (drm_dp_alternate_scrambler_reset_cap(dpcd)) { in drm_dp_link_probe()
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/linux/drivers/gpu/drm/i915/display/
A Dintel_dp_link_training.c73 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in intel_dp_read_lttpr_phy_caps()
89 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in intel_dp_read_lttpr_common_caps()
147 if (!intel_dp_read_lttpr_common_caps(intel_dp, dpcd)) in intel_dp_init_lttpr_phys()
234 if (drm_dp_read_dpcd_caps(&intel_dp->aux, dpcd)) in intel_dp_read_dprx_caps()
270 u8 dpcd[DP_RECEIVER_CAP_SIZE]; in intel_dp_init_lttpr_and_dprx_caps() local
271 int err = intel_dp_read_dprx_caps(intel_dp, dpcd); in intel_dp_init_lttpr_and_dprx_caps()
276 lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd); in intel_dp_init_lttpr_and_dprx_caps()
871 intel_dp->dpcd, dp_phy, in intel_dp_link_training_clock_recovery()
973 drm_dp_tps4_supported(intel_dp->dpcd); in intel_dp_training_pattern()
991 drm_dp_tps3_supported(intel_dp->dpcd); in intel_dp_training_pattern()
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A Dintel_dp.c1037 if (!drm_dp_is_branch(intel_dp->dpcd)) in dfp_can_convert_from_rgb()
1054 if (!drm_dp_is_branch(intel_dp->dpcd)) in dfp_can_convert_from_ycbcr444()
3190 drm_dp_is_branch(intel_dp->dpcd) && in downstream_hpd_needs_d0()
4067 drm_dp_is_branch(intel_dp->dpcd)); in intel_edp_init_dpcd()
4157 intel_dp->dpcd, in intel_dp_has_sink_count()
5029 intel_dp->dpcd[DP_DPCD_REV]); in intel_dp_process_phy_request()
5690 u8 *dpcd = intel_dp->dpcd; in intel_dp_detect_dpcd() local
5704 if (!drm_dp_is_branch(dpcd)) in intel_dp_detect_dpcd()
6114 intel_dp->dpcd, in intel_dp_detect()
6161 intel_dp->dpcd, in intel_dp_get_modes()
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A Dintel_alpm.c26 u8 dpcd; in intel_alpm_init_dpcd() local
28 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, &dpcd) < 0) in intel_alpm_init_dpcd()
31 intel_dp->alpm_dpcd = dpcd; in intel_alpm_init_dpcd()
A Dintel_dp_link_training.h16 int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE]);
/linux/drivers/gpu/drm/gma500/
A Dcdv_intel_dp.c263 uint8_t dpcd[4]; member
326 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { in cdv_intel_dp_max_lane_count()
1111 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) in cdv_intel_dp_sink_dpms()
1671 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) in cdv_dp_detect()
1673 if (intel_dp->dpcd[DP_DPCD_REV] != 0) in cdv_dp_detect()
1678 intel_dp->dpcd[0], intel_dp->dpcd[1], in cdv_dp_detect()
1679 intel_dp->dpcd[2], intel_dp->dpcd[3]); in cdv_dp_detect()
2068 intel_dp->dpcd, in cdv_intel_dp_init()
2069 sizeof(intel_dp->dpcd)); in cdv_intel_dp_init()
2079 intel_dp->dpcd[0], intel_dp->dpcd[1], in cdv_intel_dp_init()
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/linux/drivers/gpu/drm/i915/gvt/
A Ddisplay.c526 kfree(port->dpcd); in clean_virtual_dp_monitor()
527 port->dpcd = NULL; in clean_virtual_dp_monitor()
559 port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL); in setup_virtual_dp_monitor()
560 if (!port->dpcd) { in setup_virtual_dp_monitor()
569 memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE); in setup_virtual_dp_monitor()
570 port->dpcd->data_valid = true; in setup_virtual_dp_monitor()
571 port->dpcd->data[DPCD_SINK_COUNT] = 0x1; in setup_virtual_dp_monitor()
A Dhandlers.c1148 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |= in dp_aux_ch_ctl_link_training()
1154 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC; in dp_aux_ch_ctl_link_training()
1169 struct intel_vgpu_dpcd_data *dpcd = NULL; in dp_aux_ch_ctl_mmio_write() local
1200 dpcd = port->dpcd; in dp_aux_ch_ctl_mmio_write()
1249 if (dpcd && dpcd->data_valid) { in dp_aux_ch_ctl_mmio_write()
1253 dpcd->data[p] = buf[t]; in dp_aux_ch_ctl_mmio_write()
1256 dp_aux_ch_ctl_link_training(dpcd, in dp_aux_ch_ctl_mmio_write()
1264 dpcd && dpcd->data_valid); in dp_aux_ch_ctl_mmio_write()
1307 if (dpcd && dpcd->data_valid) { in dp_aux_ch_ctl_mmio_write()
1311 t = dpcd->data[addr + i - 1]; in dp_aux_ch_ctl_mmio_write()
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/linux/drivers/gpu/drm/bridge/
A Dite-it6505.c428 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
640 num, dpcd); in it6505_get_dpcd()
1462 if (it6505->dpcd[0] == 0) { in it6505_parse_link_capabilities()
1469 link->revision = it6505->dpcd[0]; in it6505_parse_link_capabilities()
2299 memset(it6505->dpcd, 0, sizeof(it6505->dpcd)); in it6505_process_hpd_irq()
2355 if (it6505->dpcd[0] == 0) { in it6505_irq_hpd()
2357 ARRAY_SIZE(it6505->dpcd)); in it6505_irq_hpd()
2387 memset(it6505->dpcd, 0, sizeof(it6505->dpcd)); in it6505_irq_hpd()
2707 memset(it6505->dpcd, 0, sizeof(it6505->dpcd)); in it6505_detect()
2767 memset(it6505->dpcd, 0, sizeof(it6505->dpcd)); in it6505_extcon_work()
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/linux/drivers/gpu/drm/nouveau/nvif/
A Doutp.c113 nvif_outp_dp_train(struct nvif_outp *outp, u8 dpcd[DP_RECEIVER_CAP_SIZE], u8 lttprs, in nvif_outp_dp_train()
126 memcpy(args.dpcd, dpcd, sizeof(args.dpcd)); in nvif_outp_dp_train()
148 args.rate[i].dpcd = rate->dpcd; in nvif_outp_dp_rates()
/linux/drivers/gpu/drm/nouveau/include/nvif/
A Doutp.h102 int dpcd; /* -1 for non-indexed rates */ member
107 int nvif_outp_dp_train(struct nvif_outp *, u8 dpcd[DP_RECEIVER_CAP_SIZE],
A Dif0012.h228 __s8 dpcd; member
243 __u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
/linux/drivers/gpu/drm/xlnx/
A Dzynqmp_dp.c317 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
697 drm_dp_link_train_clock_recovery_delay(&dp->aux, dp->dpcd); in zynqmp_dp_link_train_cr()
745 if (dp->dpcd[DP_DPCD_REV] >= DP_V1_2 && in zynqmp_dp_link_train_ce()
746 dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) in zynqmp_dp_link_train_ce()
762 drm_dp_link_train_channel_eq_delay(&dp->aux, dp->dpcd); in zynqmp_dp_link_train_ce()
796 enhanced = drm_dp_enhanced_frame_cap(dp->dpcd); in zynqmp_dp_train()
802 if (dp->dpcd[3] & 0x1) { in zynqmp_dp_train()
1548 ret = drm_dp_dpcd_read(&dp->aux, 0x0, dp->dpcd, in zynqmp_dp_bridge_detect()
1549 sizeof(dp->dpcd)); in zynqmp_dp_bridge_detect()
1556 drm_dp_max_link_rate(dp->dpcd), in zynqmp_dp_bridge_detect()
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