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Searched refs:dpp (Results 1 – 25 of 80) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
A Ddpp.h230 struct dpp *dpp,
235 struct dpp *dpp,
240 struct dpp *dpp,
244 struct dpp *dpp,
248 struct dpp *dpp,
252 struct dpp *dpp,
256 struct dpp *dpp,
261 struct dpp *dpp,
265 struct dpp *dpp,
269 struct dpp *dpp,
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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
A Ddcn10_dpp_cm.c43 dpp->tf_regs->reg
46 dpp->base.ctx
50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
129 dpp->base.ctx, in program_gamut_remap()
139 dpp->base.ctx, in program_gamut_remap()
149 dpp->base.ctx, in program_gamut_remap()
207 dpp->base.ctx, in read_gamut_remap()
217 dpp->base.ctx, in read_gamut_remap()
227 dpp->base.ctx, in read_gamut_remap()
299 dpp->base.ctx, in dpp1_cm_program_color_matrix()
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A Ddcn10_dpp.c42 dpp->tf_regs->reg
45 dpp->base.ctx
49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
125 struct dpp *dpp, in dpp1_get_optimal_number_of_taps() argument
194 dpp->filter_h = NULL; in dpp_reset()
195 dpp->filter_v = NULL; in dpp_reset()
197 memset(&dpp->scl_data, 0, sizeof(dpp->scl_data)); in dpp_reset()
198 memset(&dpp->pwl_data, 0, sizeof(dpp->pwl_data)); in dpp_reset()
237 dpp->is_write_to_ram_a_safe = !dpp->is_write_to_ram_a_safe; in dpp1_cm_set_regamma_pwl()
260 struct dpp *dpp_base, in dpp1_set_degamma_format_float()
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A Ddcn10_dpp_dscl.c44 dpp->tf_regs->reg
47 dpp->base.ctx
51 dpp->tf_shift->field_name, dpp->tf_mask->field_name
124 struct dpp *dpp_base, in dpp1_dscl_get_dscl_mode()
158 struct dpp *dpp_base, in dpp1_power_on_dscl()
180 struct dcn10_dpp *dpp, in dpp1_dscl_set_lb() argument
241 struct dcn10_dpp *dpp, in dpp1_dscl_set_scaler_filter() argument
279 struct dcn10_dpp *dpp, in dpp1_dscl_set_scl_filter() argument
341 dpp->filter_h = filter_h; in dpp1_dscl_set_scl_filter()
347 dpp->filter_v = filter_v; in dpp1_dscl_set_scl_filter()
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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
A Ddcn30_dpp_cm.c34 dpp->tf_regs->reg
37 dpp->base.ctx
41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
44 struct dpp *dpp_base) in dpp3_enable_cm_block()
78 struct dpp *dpp_base, in dpp3_program_gammcor_lut()
127 struct dpp *dpp_base, in dpp3_power_on_gamcor_lut()
146 struct dpp *dpp_base, in dpp3_program_cm_dealpha()
157 struct dpp *dpp_base, in dpp3_program_cm_bias()
169 struct dcn3_dpp *dpp, in dpp3_gamcor_reg_field() argument
352 dpp->base.ctx, in program_gamut_remap()
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A Ddcn30_dpp.c34 dpp->tf_regs->reg
37 dpp->base.ctx
41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
89 struct dpp *dpp_base, in dpp3_program_post_csc()
152 dpp->base.ctx, in dpp3_program_post_csc()
205 struct dpp *dpp_base, in dpp3_cnv_setup()
385 struct dpp *dpp_base, in dpp3_set_cursor_attributes()
419 struct dpp *dpp, in dpp3_get_optimal_number_of_taps() argument
567 struct dpp *dpp_base, in dpp3_power_on_blnd_lut()
587 struct dpp *dpp_base, in dpp3_power_on_hdr3dlut()
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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn20/
A Ddcn20_dpp_cm.c37 dpp->tf_regs->reg
43 dpp->base.ctx
47 dpp->tf_shift->field_name, dpp->tf_mask->field_name
51 struct dpp *dpp_base) in dpp2_enable_cm_block()
65 struct dpp *dpp_base, in dpp2_degamma_ram_inuse()
86 struct dpp *dpp_base, in dpp2_program_degamma_lut()
117 struct dpp *dpp_base, in dpp2_set_degamma_pwl()
135 struct dpp *dpp_base, in dpp2_set_degamma()
203 dpp->base.ctx, in program_gamut_remap()
214 struct dpp *dpp_base, in dpp2_cm_set_gamut_remap()
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A Ddcn20_dpp.c42 dpp->tf_regs->reg
45 dpp->base.ctx
49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
78 struct dpp *dpp_base, in dpp2_power_on_obuf()
93 struct dpp *dpp_base, in dpp2_dummy_program_input_lut()
98 struct dpp *dpp_base, in dpp2_cnv_setup()
317 struct dpp *dpp_base, in dpp2_cnv_set_alpha_keyer()
340 struct dpp *dpp_base, in dpp2_set_cursor_attributes()
369 struct dpp *dpp, in oppn20_dummy_program_regamma_pwl() argument
407 struct dcn20_dpp *dpp, in dpp2_construct() argument
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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn401/
A Ddcn401_dpp_cm.c43 dpp->tf_regs->reg
46 dpp->base.ctx
50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
91 void dpp401_full_bypass(struct dpp *dpp_base) in dpp401_full_bypass()
106 if (dpp->tf_mask->CM_BYPASS_EN) in dpp401_full_bypass()
116 struct dpp *dpp_base, in dpp401_set_cursor_attributes()
148 struct dpp *dpp_base, in dpp401_set_cursor_position()
163 struct dpp *dpp_base, in dpp401_set_optional_cursor_attributes()
178 struct dpp *dpp_base, in dpp401_program_cursor_csc()
234 dpp->base.ctx, in dpp401_program_cursor_csc()
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A Ddcn401_dpp_dscl.c44 dpp->tf_regs->reg
47 dpp->base.ctx
51 dpp->tf_shift->field_name, dpp->tf_mask->field_name
126 struct dpp *dpp_base, in dpp401_dscl_get_dscl_mode()
160 struct dpp *dpp_base, in dpp401_power_on_dscl()
182 struct dcn401_dpp *dpp, in dpp401_dscl_set_lb() argument
243 struct dcn401_dpp *dpp, in dpp401_dscl_set_scaler_filter() argument
281 struct dcn401_dpp *dpp, in dpp401_dscl_set_scl_filter() argument
298 if ((dpp->base.ctx->dc->config.use_spl) && (!dpp->base.ctx->dc->debug.disable_spl)) { in dpp401_dscl_set_scl_filter()
355 dpp->filter_h = filter_h; in dpp401_dscl_set_scl_filter()
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A Ddcn401_dpp.c36 dpp->tf_regs->reg
39 dpp->base.ctx
43 dpp->tf_shift->field_name, dpp->tf_mask->field_name
56 struct dpp *dpp_base, in dpp401_dpp_setup()
262 struct dcn401_dpp *dpp, in dpp401_construct() argument
269 dpp->base.ctx = ctx; in dpp401_construct()
271 dpp->base.inst = inst; in dpp401_construct()
273 dpp->base.caps = &dcn401_dpp_cap; in dpp401_construct()
275 dpp->tf_regs = tf_regs; in dpp401_construct()
276 dpp->tf_shift = tf_shift; in dpp401_construct()
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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn201/
A Ddcn201_dpp.c35 dpp->tf_regs->reg
38 dpp->base.ctx
42 dpp->tf_shift->field_name, dpp->tf_mask->field_name
45 struct dpp *dpp_base, in dpp201_cnv_setup()
191 struct dpp *dpp, in dpp201_get_optimal_number_of_taps() argument
298 struct dcn201_dpp *dpp, in dpp201_construct() argument
305 dpp->base.ctx = ctx; in dpp201_construct()
307 dpp->base.inst = inst; in dpp201_construct()
311 dpp->tf_regs = tf_regs; in dpp201_construct()
312 dpp->tf_shift = tf_shift; in dpp201_construct()
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A Ddcn201_dpp.h30 #define TO_DCN201_DPP(dpp)\ argument
31 container_of(dpp, struct dcn201_dpp, base)
58 struct dpp base;
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn35/
A Ddcn35_dpp.c31 #define REG(reg) dpp->tf_regs->reg
33 #define CTX dpp->base.ctx
41 struct dpp *dpp_base, in dpp35_dppclk_control()
45 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp35_dppclk_control() local
48 if (dpp->tf_mask->DPPCLK_RATE_CONTROL) in dpp35_dppclk_control()
63 struct dpp *dpp_base, in dpp35_program_bias_and_scale_fcnv()
66 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp35_program_bias_and_scale_fcnv() local
121 struct dcn3_dpp *dpp, struct dc_context *ctx, in dpp35_construct() argument
126 bool ret = dpp32_construct(dpp, ctx, inst, tf_regs, in dpp35_construct()
130 dpp->base.funcs = &dcn35_dpp_funcs; in dpp35_construct()
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A Ddcn35_dpp.h53 struct dpp *dpp_base,
62 void dpp35_set_fgcg(struct dcn3_dpp *dpp, bool enable);
64 void dpp35_program_bias_and_scale_fcnv(struct dpp *dpp_base,
/linux/drivers/gpu/drm/amd/display/dc/dpp/
A DMakefile31 AMD_DAL_DPP_DCN10 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn10/,$(DPP_DCN10))
39 AMD_DAL_DPP_DCN20 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn20/,$(DPP_DCN20))
47 AMD_DAL_DPP_DCN201 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn201/,$(DPP_DCN201))
55 AMD_DAL_DPP_DCN30 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn30/,$(DPP_DCN30))
63 AMD_DAL_DPP_DCN32 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn32/,$(DPP_DCN32))
71 AMD_DAL_DPP_DCN35 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn35/,$(DPP_DCN35))
79 AMD_DAL_DPP_DCN401 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn401/,$(DPP_DCN401))
/linux/Documentation/devicetree/bindings/media/i2c/
A Dadv7604.yaml36 - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
37 - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
38 - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
39 - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
40 - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
41 - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
42 - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
43 - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
44 - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
45 - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn32/
A Ddcn32_dpp.c147 struct dcn3_dpp *dpp, in dpp32_construct() argument
154 dpp->base.ctx = ctx; in dpp32_construct()
156 dpp->base.inst = inst; in dpp32_construct()
157 dpp->base.funcs = &dcn32_dpp_funcs; in dpp32_construct()
158 dpp->base.caps = &dcn32_dpp_cap; in dpp32_construct()
160 dpp->tf_regs = tf_regs; in dpp32_construct()
161 dpp->tf_shift = tf_shift; in dpp32_construct()
162 dpp->tf_mask = tf_mask; in dpp32_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/
A Ddcn201_resource.c622 static void dcn201_dpp_destroy(struct dpp **dpp) in dcn201_dpp_destroy() argument
624 kfree(TO_DCN201_DPP(*dpp)); in dcn201_dpp_destroy()
625 *dpp = NULL; in dcn201_dpp_destroy()
632 struct dcn201_dpp *dpp = in dcn201_dpp_create() local
635 if (!dpp) in dcn201_dpp_create()
640 return &dpp->base; in dcn201_dpp_create()
642 kfree(dpp); in dcn201_dpp_create()
1121 dc->caps.color.dpp.dcn_arch = 1; in dcn201_resource_construct()
1123 dc->caps.color.dpp.icsc = 1; in dcn201_resource_construct()
1124 dc->caps.color.dpp.dgam_ram = 1; in dcn201_resource_construct()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
A Ddcn10_hwseq.c301 struct dpp *dpp = pool->dpps[i]; in dcn10_log_color_state() local
304 dpp->funcs->dpp_read_state(dpp, &s); in dcn10_log_color_state()
1273 struct dpp *dpp, in dcn10_plane_atomic_power_down() argument
1289 dpp->funcs->dpp_reset(dpp); in dcn10_plane_atomic_power_down()
1308 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn10_plane_atomic_disable() local
1450 dpp->funcs->dpp_reset(dpp); in dcn10_init_pipes()
1456 pipe_ctx->plane_res.dpp = dpp; in dcn10_init_pipes()
1895 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn10_set_output_transfer_func() local
2650 dpp->funcs->dpp_setup(dpp, in dcn10_update_dpp()
2772 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn10_update_dchubp_dpp() local
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn10/
A Ddcn10_resource.c575 static void dcn10_dpp_destroy(struct dpp **dpp) in dcn10_dpp_destroy() argument
577 kfree(TO_DCN10_DPP(*dpp)); in dcn10_dpp_destroy()
578 *dpp = NULL; in dcn10_dpp_destroy()
585 struct dcn10_dpp *dpp = in dcn10_dpp_create() local
588 if (!dpp) in dcn10_dpp_create()
591 dpp1_construct(dpp, ctx, inst, in dcn10_dpp_create()
593 return &dpp->base; in dcn10_dpp_create()
1367 dc->caps.color.dpp.dcn_arch = 1; in dcn10_resource_construct()
1369 dc->caps.color.dpp.icsc = 1; in dcn10_resource_construct()
1370 dc->caps.color.dpp.dgam_ram = 1; in dcn10_resource_construct()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
A Ddcn30_hwseq.c87 struct dpp *dpp = pool->dpps[i]; in dcn30_log_color_state() local
90 dpp->funcs->dpp_read_state(dpp, &s); in dcn30_log_color_state()
91 dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap); in dcn30_log_color_state()
101 dpp->inst, in dcn30_log_color_state()
148 dc->caps.color.dpp.icsc, in dcn30_log_color_state()
149 dc->caps.color.dpp.dgam_ram, in dcn30_log_color_state()
160 dc->caps.color.dpp.ocsc); in dcn30_log_color_state()
224 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_blend_lut()
246 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_mpc_shaper_3dlut()
301 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_input_transfer_func()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/
A Ddcn301_resource.c709 static void dcn301_dpp_destroy(struct dpp **dpp) in dcn301_dpp_destroy() argument
711 kfree(TO_DCN20_DPP(*dpp)); in dcn301_dpp_destroy()
712 *dpp = NULL; in dcn301_dpp_destroy()
717 struct dcn3_dpp *dpp = in dcn301_dpp_create() local
720 if (!dpp) in dcn301_dpp_create()
725 return &dpp->base; in dcn301_dpp_create()
728 kfree(dpp); in dcn301_dpp_create()
1450 dc->caps.color.dpp.dcn_arch = 1; in dcn301_resource_construct()
1452 dc->caps.color.dpp.icsc = 1; in dcn301_resource_construct()
1459 dc->caps.color.dpp.post_csc = 1; in dcn301_resource_construct()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/
A Ddcn302_resource.c542 if (!dpp) in dcn302_dpp_create()
546 return &dpp->base; in dcn302_dpp_create()
549 kfree(dpp); in dcn302_dpp_create()
1239 dc->caps.color.dpp.dcn_arch = 1; in dcn302_resource_construct()
1240 dc->caps.color.dpp.input_lut_shared = 0; in dcn302_resource_construct()
1241 dc->caps.color.dpp.icsc = 1; in dcn302_resource_construct()
1248 dc->caps.color.dpp.post_csc = 1; in dcn302_resource_construct()
1249 dc->caps.color.dpp.gamma_corr = 1; in dcn302_resource_construct()
1252 dc->caps.color.dpp.hw_3d_lut = 1; in dcn302_resource_construct()
1253 dc->caps.color.dpp.ogam_ram = 1; in dcn302_resource_construct()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/
A Ddcn303_resource.c521 if (!dpp) in dcn303_dpp_create()
525 return &dpp->base; in dcn303_dpp_create()
528 kfree(dpp); in dcn303_dpp_create()
1184 dc->caps.color.dpp.dcn_arch = 1; in dcn303_resource_construct()
1185 dc->caps.color.dpp.input_lut_shared = 0; in dcn303_resource_construct()
1186 dc->caps.color.dpp.icsc = 1; in dcn303_resource_construct()
1193 dc->caps.color.dpp.post_csc = 1; in dcn303_resource_construct()
1194 dc->caps.color.dpp.gamma_corr = 1; in dcn303_resource_construct()
1197 dc->caps.color.dpp.hw_3d_lut = 1; in dcn303_resource_construct()
1198 dc->caps.color.dpp.ogam_ram = 1; in dcn303_resource_construct()
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