Searched refs:dram_info (Results 1 – 9 of 9) sorted by relevance
380 struct dram_info *dram_info = &i915->dram_info; in skl_dram_get_channels_info() local389 dram_info->num_channels++; in skl_dram_get_channels_info()395 dram_info->num_channels++; in skl_dram_get_channels_info()443 struct dram_info *dram_info = &i915->dram_info; in skl_get_dram_info() local537 struct dram_info *dram_info = &i915->dram_info; in bxt_get_dram_info() local553 dram_info->num_channels++; in bxt_get_dram_info()560 dram_info->type != type); in bxt_get_dram_info()572 dram_info->type = type; in bxt_get_dram_info()585 struct dram_info *dram_info = &dev_priv->dram_info; in icl_pcode_read_mem_global_info() local665 struct dram_info *dram_info = &i915->dram_info; in xelpdp_get_dram_info() local[all …]
219 const struct dram_info *dram_info = &dev_priv->dram_info; in icl_get_qgv_points() local222 qi->num_points = dram_info->num_qgv_points; in icl_get_qgv_points()223 qi->num_psf_points = dram_info->num_psf_gv_points; in icl_get_qgv_points()226 switch (dram_info->type) { in icl_get_qgv_points()250 MISSING_CASE(dram_info->type); in icl_get_qgv_points()254 switch (dram_info->type) { in icl_get_qgv_points()288 qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8; in icl_get_qgv_points()405 int num_channels = max_t(u8, 1, dev_priv->dram_info.num_channels); in icl_get_bw_info()473 const struct dram_info *dram_info = &dev_priv->dram_info; in tgl_get_bw_info() local491 (dram_info->type == INTEL_DRAM_LPDDR4 || dram_info->type == INTEL_DRAM_LPDDR5)) in tgl_get_bw_info()[all …]
1581 enum intel_dram_type type = dev_priv->dram_info.type; in tgl_bw_buddy_init()1582 u8 num_channels = dev_priv->dram_info.num_channels; in tgl_bw_buddy_init()
3262 return i915->dram_info.symmetric_memory; in skl_watermark_ipc_can_enable()3281 bool wm_lv_0_adjust_needed = i915->dram_info.wm_lv_0_adjust_needed; in adjust_wm_latency()
743 struct iwl_dram_info *dram_info) in iwl_dbg_tlv_update_dram() argument770 data = &dram_info->dram_frags[alloc_id - 1]; in iwl_dbg_tlv_update_dram()798 struct iwl_dram_info *dram_info; in iwl_dbg_tlv_update_drams() local803 dram_info = frags->block; in iwl_dbg_tlv_update_drams()809 memset(dram_info, 0, sizeof(*dram_info)); in iwl_dbg_tlv_update_drams()817 ret = iwl_dbg_tlv_update_dram(fwrt, i, dram_info); in iwl_dbg_tlv_update_drams()827 dram_info->first_word = cpu_to_le32(DRAM_INFO_FIRST_MAGIC_WORD); in iwl_dbg_tlv_update_drams()900 struct iwl_dbgc1_info dram_info = {}; in iwl_dbg_tlv_apply_config() local920 dram_info.dbgc1_add_lsb = in iwl_dbg_tlv_apply_config()922 dram_info.dbgc1_add_msb = in iwl_dbg_tlv_apply_config()[all …]
505 struct dram_info { struct521 } dram_info; member
275 struct iwl_dram_sec_info dram_info; member297 struct iwl_dram_sec_info dram_info; member
296 struct dram_info { struct312 } dram_info; member
494 offsetofend(struct iwl_tx_cmd_gen2, dram_info) > in iwl_txq_gen2_build_tfd()498 offsetofend(struct iwl_tx_cmd_gen3, dram_info) > in iwl_txq_gen2_build_tfd()
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