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Searched refs:dram_speed_mts (Results 1 – 25 of 26) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/dml2/
A Ddml2_policy.c37 entry->dram_speed_mts = bw_on_sdp / (socbb->num_chans * in get_optimal_ntuple()
45 } else if (entry->dram_speed_mts > 0) { in get_optimal_ntuple()
104 table->state_array[index].dram_speed_mts = (int)entry->dram_speed_mts; in insert_entry_into_table_sorted()
156 if (p->in_states->state_array[i].dram_speed_mts > 0) in dml2_policy_build_synthetic_soc_states()
180 s->entry.dram_speed_mts = 0; in dml2_policy_build_synthetic_soc_states()
191 s->entry.dram_speed_mts = p->in_states->state_array[i].dram_speed_mts; in dml2_policy_build_synthetic_soc_states()
206 s->entry.dram_speed_mts = 0; in dml2_policy_build_synthetic_soc_states()
215 s->entry.dram_speed_mts = 0; in dml2_policy_build_synthetic_soc_states()
235 … if (p->in_states->state_array[j].dram_speed_mts >= p->out_states->state_array[i].dram_speed_mts) { in dml2_policy_build_synthetic_soc_states()
236 p->out_states->state_array[i].dram_speed_mts = p->in_states->state_array[j].dram_speed_mts; in dml2_policy_build_synthetic_soc_states()
[all …]
A Ddml2_translation_helper.c367 p->in_states->state_array[0].dram_speed_mts = 100 * transactions_per_mem_clock; in dml2_init_soc_states()
387 p->in_states->state_array[1].dram_speed_mts = 1125 * transactions_per_mem_clock; in dml2_init_soc_states()
403 p->in_states->state_array[0].dram_speed_mts = 100 * transactions_per_mem_clock; in dml2_init_soc_states()
423 p->in_states->state_array[1].dram_speed_mts = 1000 * transactions_per_mem_clock; in dml2_init_soc_states()
438 p->in_states->state_array[0].dram_speed_mts = 97 * transactions_per_mem_clock; //100 * in dml2_init_soc_states()
458 p->in_states->state_array[1].dram_speed_mts = 1125 * transactions_per_mem_clock; in dml2_init_soc_states()
533 p->in_states->state_array[i].dram_speed_mts = in dml2_init_soc_states()
678 out->state_array[i].dram_speed_mts = dc->dml.soc.clock_limits[i].dram_speed_mts; in dml2_translate_soc_states()
A Ddml2_wrapper.c284 …>v20.dml_core_ctx.states.state_array[result].dram_speed_mts < s_global->dummy_pstate_table[i].dram… in calculate_lowest_supported_state_for_temp_read()
581 …clk_mts = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dram_speed_mts; in dml2_validate_and_build_resource()
639 …clk_mts = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dram_speed_mts; in dml2_validate_and_build_resource()
A Ddisplay_mode_util.c633 dml_print("DML: state_bbox: dram_speed_mts = %f\n", state->dram_speed_mts); in dml_print_soc_state_bounding_box()
A Ddisplay_mode_core_structs.h277 dml_float_t dram_speed_mts; member
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn321/
A Ddcn321_fpu.c118 .dram_speed_mts = 16000.0,
176 } else if (entry->dram_speed_mts > 0) { in get_optimal_ntuple()
301 if ((table[i].dram_speed_mts > table[i+1].dram_speed_mts) || in remove_inconsistent_entries()
437 entry.dram_speed_mts = 0; in build_synthetic_soc_states()
447 entry.dram_speed_mts = 0; in build_synthetic_soc_states()
469 entry.dram_speed_mts = 0; in build_synthetic_soc_states()
480 entry.dram_speed_mts = 0; in build_synthetic_soc_states()
563 table[i].dram_speed_mts == table[i + 1].dram_speed_mts) in build_synthetic_soc_states()
844 if (!dram_speed_mts[i] && i > 0) in dcn321_update_bw_bounding_box_fpu()
845 dcn3_21_soc.clock_limits[i].dram_speed_mts = dcn3_21_soc.clock_limits[i-1].dram_speed_mts; in dcn321_update_bw_bounding_box_fpu()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn303/
A Ddcn303_fpu.c197 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn303_fpu_update_bw_bounding_box() local
290 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn303_fpu_update_bw_bounding_box()
294 dram_speed_mts[num_states++] = in dcn303_fpu_update_bw_bounding_box()
304 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn303_fpu_update_bw_bounding_box()
310 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn303_fpu_update_bw_bounding_box()
328 dcn3_03_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; in dcn303_fpu_update_bw_bounding_box()
351 if (dcn3_03_soc.clock_limits[i].dram_speed_mts > 1700) in dcn303_fpu_update_bw_bounding_box()
354 if (dcn3_03_soc.clock_limits[i].dram_speed_mts >= 1500) { in dcn303_fpu_update_bw_bounding_box()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn302/
A Ddcn302_fpu.c201 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn302_fpu_update_bw_bounding_box() local
285 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn302_fpu_update_bw_bounding_box()
289 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn302_fpu_update_bw_bounding_box()
298 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn302_fpu_update_bw_bounding_box()
304 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn302_fpu_update_bw_bounding_box()
322 dcn3_02_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; in dcn302_fpu_update_bw_bounding_box()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/
A Ddcn301_fpu.c116 .dram_speed_mts = 2400.0,
128 .dram_speed_mts = 2400.0,
140 .dram_speed_mts = 4267.0,
152 .dram_speed_mts = 4267.0,
164 .dram_speed_mts = 4267.0,
354 s[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; in dcn301_fpu_update_bw_bounding_box()
394 …_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0; in dcn301_fpu_set_wm_ranges()
395 ranges->reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16; in dcn301_fpu_set_wm_ranges()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn351/
A Ddcn351_fpu.c104 .dram_speed_mts = 3200.0,
117 .dram_speed_mts = 6400.0,
130 .dram_speed_mts = 7500.0,
143 .dram_speed_mts = 7500.0,
156 .dram_speed_mts = 8533.0,
169 .dram_speed_mts = 8533.0,
182 .dram_speed_mts = 8533.0,
195 .dram_speed_mts = 8533.0,
322 clock_limits[i].dram_speed_mts = in dcn351_update_bw_bounding_box_fpu()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddcn20_fpu.c233 .dram_speed_mts = 8960.0,
244 .dram_speed_mts = 11104.0,
255 .dram_speed_mts = 14000.0,
344 .dram_speed_mts = 8960.0,
455 .dram_speed_mts = 1069.0,
466 .dram_speed_mts = 1324.0,
477 .dram_speed_mts = 1670.0,
488 .dram_speed_mts = 2000.0,
499 .dram_speed_mts = 2000.0,
510 .dram_speed_mts = 2000.0,
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddcn30_fpu.c504 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dram_speed_mts) in dcn30_fpu_calculate_wm_and_dlg()
579 if (dc->dml.soc.clock_limits[i].dram_speed_mts > 1700) { in dcn30_fpu_calculate_wm_and_dlg()
580 context->bw_ctx.dml.vba.DRAMSpeed = dc->dml.soc.clock_limits[i].dram_speed_mts; in dcn30_fpu_calculate_wm_and_dlg()
647 unsigned int *dram_speed_mts) in dcn30_fpu_update_bw_bounding_box() argument
660 dcn3_0_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; in dcn30_fpu_update_bw_bounding_box()
774 base->bw_params->dummy_pstate_table[0].dram_speed_mts = 1600; in dcn3_fpu_build_wm_range_table()
776 base->bw_params->dummy_pstate_table[1].dram_speed_mts = 8000; in dcn3_fpu_build_wm_range_table()
778 base->bw_params->dummy_pstate_table[2].dram_speed_mts = 10000; in dcn3_fpu_build_wm_range_table()
780 base->bw_params->dummy_pstate_table[3].dram_speed_mts = 16000; in dcn3_fpu_build_wm_range_table()
A Ddcn30_fpu.h64 unsigned int *dram_speed_mts);
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddcn32_fpu.c139 .dram_speed_mts = 18000.0,
408 } else if (entry->dram_speed_mts > 0) { in get_optimal_ntuple()
2753 if ((table[i].dram_speed_mts > table[i+1].dram_speed_mts) || in remove_inconsistent_entries()
2889 entry.dram_speed_mts = 0; in build_synthetic_soc_states()
2899 entry.dram_speed_mts = 0; in build_synthetic_soc_states()
2921 entry.dram_speed_mts = 0; in build_synthetic_soc_states()
2932 entry.dram_speed_mts = 0; in build_synthetic_soc_states()
3013 table[i].dram_speed_mts == table[i + 1].dram_speed_mts) in build_synthetic_soc_states()
3288 if (!dram_speed_mts[i] && i > 0) in dcn32_update_bw_bounding_box_fpu()
3289 dcn3_2_soc.clock_limits[i].dram_speed_mts = dcn3_2_soc.clock_limits[i-1].dram_speed_mts; in dcn32_update_bw_bounding_box_fpu()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn401/
A Ddcn401_fpu.c73 …clk_mgr->bw_params->dummy_pstate_table[0].dram_speed_mts = clk_mgr->bw_params->clk_table.entries[0… in dcn401_build_wm_range_table_fpu()
75 …clk_mgr->bw_params->dummy_pstate_table[1].dram_speed_mts = clk_mgr->bw_params->clk_table.entries[1… in dcn401_build_wm_range_table_fpu()
77 …clk_mgr->bw_params->dummy_pstate_table[2].dram_speed_mts = clk_mgr->bw_params->clk_table.entries[2… in dcn401_build_wm_range_table_fpu()
79 …clk_mgr->bw_params->dummy_pstate_table[3].dram_speed_mts = clk_mgr->bw_params->clk_table.entries[3… in dcn401_build_wm_range_table_fpu()
/linux/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_socbb.h31 uint32_t dram_speed_mts; member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
A Ddcn35_clk_mgr.c795 uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[i]); in dcn35_clk_mgr_helper_populate_bw_params() local
797 if (is_valid_clock_value(dram_speed_mts) && dram_speed_mts > max_dram_speed_mts) { in dcn35_clk_mgr_helper_populate_bw_params()
798 max_dram_speed_mts = dram_speed_mts; in dcn35_clk_mgr_helper_populate_bw_params()
807 uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[i]); in dcn35_clk_mgr_helper_populate_bw_params() local
809 if (is_valid_clock_value(dram_speed_mts) && dram_speed_mts < min_dram_speed_mts) { in dcn35_clk_mgr_helper_populate_bw_params()
810 min_dram_speed_mts = dram_speed_mts; in dcn35_clk_mgr_helper_populate_bw_params()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/
A Ddcn201_resource.c149 .dram_speed_mts = 2000.0,
160 .dram_speed_mts = 3600.0,
171 .dram_speed_mts = 6800.0,
182 .dram_speed_mts = 14000.0,
194 .dram_speed_mts = 14000.0,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
A Ddcn31_fpu.c632 s[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * in dcn31_update_bw_bounding_box()
700 …dcn3_15_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->ent… in dcn315_update_bw_bounding_box()
772 s[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * in dcn316_update_bw_bounding_box()
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dclk_mgr.h244 unsigned int dram_speed_mts; member
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/
A Ddcn30_resource.c2106 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box() local
2199 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn30_update_bw_bounding_box()
2203 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn30_update_bw_bounding_box()
2212 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn30_update_bw_bounding_box()
2218 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn30_update_bw_bounding_box()
2223 dcn30_fpu_update_bw_bounding_box(dc, bw_params, &dcn30_bb_max_clk, dcfclk_mhz, dram_speed_mts); in dcn30_update_bw_bounding_box()
/linux/drivers/gpu/drm/amd/display/dc/dml/
A Ddisplay_mode_structs.h163 double dram_speed_mts; member
A Ddisplay_mode_vba.c382 mode_lib->vba.DRAMSpeed = soc->clock_limits[i].dram_speed_mts; in fetch_socbb_params()
403 mode_lib->vba.DRAMSpeedPerState[i] = soc->clock_limits[i].dram_speed_mts; in fetch_socbb_params()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/
A Ddcn314_fpu.c241 …clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_… in dcn314_update_bw_bounding_box_fpu()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/
A Ddcn35_fpu.c288 clock_limits[i].dram_speed_mts = in dcn35_update_bw_bounding_box_fpu()

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