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Searched refs:dsc (Results 1 – 25 of 139) sorted by relevance

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/linux/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_hw_dsc_1_2.c99 if (!hw_dsc || !dsc) in dpu_hw_dsc_config_1_2()
131 if (dsc->native_422) in dpu_hw_dsc_config_1_2()
133 if (dsc->native_420) in dpu_hw_dsc_config_1_2()
137 bpp = dsc->bits_per_pixel; in dpu_hw_dsc_config_1_2()
141 if (dsc->native_422 || dsc->native_420) in dpu_hw_dsc_config_1_2()
146 if (dsc->block_pred_enable) in dpu_hw_dsc_config_1_2()
149 if (dsc->convert_rgb) in dpu_hw_dsc_config_1_2()
223 if (dsc->native_422) in dpu_hw_dsc_config_1_2()
225 else if (dsc->native_420) in dpu_hw_dsc_config_1_2()
227 if (!dsc->convert_rgb) in dpu_hw_dsc_config_1_2()
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A Ddpu_hw_dsc.c69 data |= (dsc->simple_422 << 2); in dpu_hw_dsc_config()
70 data |= (dsc->convert_rgb << 1); in dpu_hw_dsc_config()
75 data = dsc->pic_width << 16; in dpu_hw_dsc_config()
76 data |= dsc->pic_height; in dpu_hw_dsc_config()
79 data = dsc->slice_width << 16; in dpu_hw_dsc_config()
80 data |= dsc->slice_height; in dpu_hw_dsc_config()
103 data |= dsc->slice_bpg_offset; in dpu_hw_dsc_config()
107 data |= dsc->final_offset; in dpu_hw_dsc_config()
113 data |= dsc->flatness_min_qp; in dpu_hw_dsc_config()
116 data = dsc->rc_model_size; in dpu_hw_dsc_config()
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A Ddpu_hw_dsc.h37 struct drm_dsc_config *dsc,
47 struct drm_dsc_config *dsc);
91 void dpu_hw_dsc_destroy(struct dpu_hw_dsc *dsc);
/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn35/
A Ddcn35_dsc.c57 dsc->ctx->logger
59 void dsc35_construct(struct dcn20_dsc *dsc, in dsc35_construct() argument
66 dsc->base.ctx = ctx; in dsc35_construct()
67 dsc->base.inst = inst; in dsc35_construct()
68 dsc->base.funcs = &dcn35_dsc_funcs; in dsc35_construct()
70 dsc->dsc_regs = dsc_regs; in dsc35_construct()
71 dsc->dsc_shift = (const struct dcn20_dsc_shift *)(dsc_shift); in dsc35_construct()
72 dsc->dsc_mask = (const struct dcn20_dsc_mask *)(dsc_mask); in dsc35_construct()
74 dsc->max_image_width = 5184; in dsc35_construct()
79 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); in dsc35_enable()
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/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn401/
A Ddcn401_dsc.c53 dsc->ctx->logger
71 dsc->base.ctx = ctx; in dsc401_construct()
72 dsc->base.inst = inst; in dsc401_construct()
73 dsc->base.funcs = &dcn401_dsc_funcs; in dsc401_construct()
75 dsc->dsc_regs = dsc_regs; in dsc401_construct()
76 dsc->dsc_shift = dsc_shift; in dsc401_construct()
77 dsc->dsc_mask = dsc_mask; in dsc401_construct()
79 dsc->max_image_width = 5184; in dsc401_construct()
155 dsc_config_log(dsc, dsc_cfg); in dsc401_set_config()
159 dsc_log_pps(dsc, &dsc401->reg_vals.pps); in dsc401_set_config()
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/linux/drivers/gpu/drm/amd/display/dc/dsc/
A Ddsc.h101 void (*dsc_read_state)(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
102 …bool (*dsc_validate_stream)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cf…
103 void (*dsc_set_config)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
105 bool (*dsc_get_packed_pps)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
107 void (*dsc_enable)(struct display_stream_compressor *dsc, int opp_pipe);
108 void (*dsc_disable)(struct display_stream_compressor *dsc);
109 void (*dsc_disconnect)(struct display_stream_compressor *dsc);
110 void (*dsc_wait_disconnect_pending_clear)(struct display_stream_compressor *dsc);
A DMakefile11 AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/dsc/dcn20/,$(DSC_DCN20))
22 AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/dsc/dcn35/,$(DSC_DCN35))
30 AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/dsc/dcn401/,$(DSC_DCN401))
36 AMD_DAL_DSC = $(addprefix $(AMDDALPATH)/dc/dsc/,$(DSC))
/linux/drivers/gpu/drm/panel/
A Dpanel-visionox-r66451.c184 if (!dsi->dsc) { in visionox_r66451_enable()
282 struct drm_dsc_config *dsc; in visionox_r66451_probe() local
289 dsc = devm_kzalloc(dev, sizeof(*dsc), GFP_KERNEL); in visionox_r66451_probe()
290 if (!dsc) in visionox_r66451_probe()
294 dsc->dsc_version_major = 0x1; in visionox_r66451_probe()
295 dsc->dsc_version_minor = 0x2; in visionox_r66451_probe()
297 dsc->slice_height = 20; in visionox_r66451_probe()
298 dsc->slice_width = 540; in visionox_r66451_probe()
299 dsc->slice_count = 2; in visionox_r66451_probe()
300 dsc->bits_per_component = 8; in visionox_r66451_probe()
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A Dpanel-lg-sw43408.c33 struct drm_dsc_config dsc; member
106 drm_dsc_pps_payload_pack(&pps, sw43408->link->dsc); in sw43408_program()
276 ctx->dsc.dsc_version_major = 0x1; in sw43408_probe()
277 ctx->dsc.dsc_version_minor = 0x1; in sw43408_probe()
280 ctx->dsc.slice_height = 16; in sw43408_probe()
281 ctx->dsc.slice_width = 540; in sw43408_probe()
282 ctx->dsc.slice_count = 2; in sw43408_probe()
283 ctx->dsc.bits_per_component = 8; in sw43408_probe()
284 ctx->dsc.bits_per_pixel = 8 << 4; in sw43408_probe()
285 ctx->dsc.block_pred_enable = true; in sw43408_probe()
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A Dpanel-raydium-rm692e5.c23 struct drm_dsc_config dsc; member
154 drm_dsc_pps_payload_pack(&pps, &ctx->dsc); in rm692e5_prepare()
321 dsi->dsc = &ctx->dsc; in rm692e5_probe()
324 ctx->dsc.dsc_version_major = 1; in rm692e5_probe()
325 ctx->dsc.dsc_version_minor = 1; in rm692e5_probe()
326 ctx->dsc.slice_height = 60; in rm692e5_probe()
327 ctx->dsc.slice_width = 1224; in rm692e5_probe()
329 ctx->dsc.slice_count = 1224 / ctx->dsc.slice_width; in rm692e5_probe()
330 ctx->dsc.bits_per_component = 8; in rm692e5_probe()
331 ctx->dsc.bits_per_pixel = 8 << 4; /* 4 fractional bits */ in rm692e5_probe()
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/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn20/
A Ddcn20_dsc.c58 dsc->ctx->logger
76 dsc->base.ctx = ctx; in dsc2_construct()
77 dsc->base.inst = inst; in dsc2_construct()
78 dsc->base.funcs = &dcn20_dsc_funcs; in dsc2_construct()
80 dsc->dsc_regs = dsc_regs; in dsc2_construct()
81 dsc->dsc_shift = dsc_shift; in dsc2_construct()
82 dsc->dsc_mask = dsc_mask; in dsc2_construct()
84 dsc->max_image_width = 5184; in dsc2_construct()
196 dsc_config_log(dsc, dsc_cfg); in dsc2_set_config()
215 dsc_config_log(dsc, dsc_cfg); in dsc2_get_packed_pps()
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A Ddcn20_dsc.h31 #define TO_DCN20_DSC(dsc)\ argument
32 container_of(dsc, struct dcn20_dsc, base)
566 void dsc_config_log(struct display_stream_compressor *dsc,
569 void dsc_log_pps(struct display_stream_compressor *dsc,
588 void dsc2_construct(struct dcn20_dsc *dsc,
598 bool dsc2_get_packed_pps(struct display_stream_compressor *dsc,
602 void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
606 void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe);
607 void dsc2_disable(struct display_stream_compressor *dsc);
608 void dsc2_disconnect(struct display_stream_compressor *dsc);
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/linux/drivers/gpu/drm/msm/
A Dmsm_dsc_helper.h21 static inline u32 msm_dsc_get_slices_per_intf(const struct drm_dsc_config *dsc, u32 intf_width) in msm_dsc_get_slices_per_intf() argument
23 return DIV_ROUND_UP(intf_width, dsc->slice_width); in msm_dsc_get_slices_per_intf()
33 static inline u32 msm_dsc_get_bytes_per_line(const struct drm_dsc_config *dsc) in msm_dsc_get_bytes_per_line() argument
35 return dsc->slice_count * dsc->slice_chunk_size; in msm_dsc_get_bytes_per_line()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn314/
A Ddcn314_hwseq.c74 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in update_dsc_on_stream() local
79 ASSERT(dsc); in update_dsc_on_stream()
98 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); in update_dsc_on_stream()
99 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); in update_dsc_on_stream()
125 dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); in update_dsc_on_stream()
127 ASSERT(odm_pipe->stream_res.dsc); in update_dsc_on_stream()
128 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); in update_dsc_on_stream()
183 if (pipe_ctx->stream_res.dsc) { in dcn314_update_odm()
190 current_pipe_ctx->next_odm_pipe->stream_res.dsc) { in dcn314_update_odm()
191 struct display_stream_compressor *dsc = current_pipe_ctx->next_odm_pipe->stream_res.dsc; in dcn314_update_odm() local
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/linux/drivers/gpu/drm/msm/dsi/
A Ddsi_host.c555 if (dsc) in dsi_get_pclk_rate()
851 struct drm_dsc_config *dsc = msm_host->dsc; in dsi_update_dsc_timing() local
946 struct drm_dsc_config *dsc = msm_host->dsc; in dsi_timing_setup() local
958 DBG("Mode %dx%d\n", dsc->pic_width, dsc->pic_height); in dsi_timing_setup()
993 if (msm_host->dsc) in dsi_timing_setup()
1014 if (msm_host->dsc) in dsi_timing_setup()
1633 if (dsi->dsc) in dsi_host_attach()
1634 msm_host->dsc = dsi->dsc; in dsi_host_attach()
1789 dsc->initial_scale_value = drm_dsc_initial_scale_value(dsc); in dsi_populate_dsc_params()
1790 dsc->line_buf_depth = dsc->bits_per_component + 1; in dsi_populate_dsc_params()
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/linux/drivers/gpu/drm/i915/display/
A Dintel_vdsc.c273 pipe_config->dsc.slice_count); in intel_dsc_compute_params()
376 return crtc_state->dsc.dsc_split ? 2 : 1; in intel_dsc_get_vdsc_per_pipe()
692 if (!crtc_state->dsc.compression_enable) in intel_dsc_dsi_pps_write()
712 if (!crtc_state->dsc.compression_enable) in intel_dsc_dp_pps_write()
762 if (!crtc_state->dsc.compression_enable) in intel_dsc_enable()
787 if (old_crtc_state->dsc.compression_enable || in intel_dsc_disable()
963 if (!crtc_state->dsc.compression_enable) in intel_dsc_get_config()
979 FXP_Q4_ARGS(crtc_state->dsc.compressed_bpp_x16), in intel_vdsc_dump_state()
980 crtc_state->dsc.slice_count, in intel_vdsc_dump_state()
981 str_yes_no(crtc_state->dsc.dsc_split)); in intel_vdsc_dump_state()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
A Ddcn35_hwseq.c322 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in update_dsc_on_stream() local
329 ASSERT(dsc); in update_dsc_on_stream()
339 if (!dsc) { in update_dsc_on_stream()
345 dsc->funcs->dsc_read_state(dsc, &dsc_state); in update_dsc_on_stream()
361 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); in update_dsc_on_stream()
362 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); in update_dsc_on_stream()
388 dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); in update_dsc_on_stream()
391 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); in update_dsc_on_stream()
454 struct display_stream_compressor *dsc = current_pipe_ctx->next_odm_pipe->stream_res.dsc; in dcn35_update_odm() local
456 dsc->funcs->dsc_disconnect(dsc); in dcn35_update_odm()
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/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm_debugfs.c1557 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_clock_en_read()
1559 dsc->funcs->dsc_read_state(dsc, &dsc_state); in dp_dsc_clock_en_read()
1747 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_slice_width_read()
1749 dsc->funcs->dsc_read_state(dsc, &dsc_state); in dp_dsc_slice_width_read()
1935 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_slice_height_read()
1937 dsc->funcs->dsc_read_state(dsc, &dsc_state); in dp_dsc_slice_height_read()
2119 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_bits_per_pixel_read()
2298 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_pic_width_read()
2356 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_pic_height_read()
2429 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_chunk_size_read()
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/linux/drivers/net/ethernet/broadcom/
A Dsb1250-mac.c775 struct sbdmadscr *dsc; in sbdma_add_rcvbuffer() local
782 dsc = d->sbdma_addptr; in sbdma_add_rcvbuffer()
848 dsc->dscr_b = 0; in sbdma_add_rcvbuffer()
889 struct sbdmadscr *dsc; in sbdma_add_txbuffer() local
897 dsc = d->sbdma_addptr; in sbdma_add_txbuffer()
928 dsc->dscr_a = phys | in sbdma_add_txbuffer()
1058 struct sbdmadscr *dsc; in sbdma_rx_process() local
1084 dsc = d->sbdma_remptr; in sbdma_rx_process()
1085 curidx = dsc - d->sbdma_dscrtable; in sbdma_rx_process()
1087 prefetch(dsc); in sbdma_rx_process()
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/linux/drivers/gpu/drm/tests/
A Ddrm_dp_mst_helper_test.c18 const bool dsc; member
26 .dsc = false,
32 .dsc = false,
38 .dsc = false,
44 .dsc = true,
50 .dsc = true,
65 sprintf(desc, "Clock %d BPP %d DSC %s", t->clock, t->bpp, t->dsc ? "enabled" : "disabled"); in dp_mst_calc_pbn_mode_desc()
/linux/include/linux/irqchip/
A Dirq-partition-percpu.h28 struct irq_domain *partition_get_domain(struct partition_desc *dsc);
47 struct irq_domain *partition_get_domain(struct partition_desc *dsc) in partition_get_domain() argument
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
A Ddcn32_hwseq.c1009 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in dcn32_update_dsc_on_stream() local
1027 ASSERT(dsc); in dcn32_update_dsc_on_stream()
1037 if (!dsc) { in dcn32_update_dsc_on_stream()
1043 dsc->funcs->dsc_read_state(dsc, &dsc_state); in dcn32_update_dsc_on_stream()
1062 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); in dcn32_update_dsc_on_stream()
1063 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); in dcn32_update_dsc_on_stream()
1087 dsc->funcs->dsc_disconnect(pipe_ctx->stream_res.dsc); in dcn32_update_dsc_on_stream()
1090 odm_pipe->stream_res.dsc->funcs->dsc_disconnect(odm_pipe->stream_res.dsc); in dcn32_update_dsc_on_stream()
1151 if (pipe_ctx->stream_res.dsc) { in dcn32_update_odm()
1159 struct display_stream_compressor *dsc = current_pipe_ctx->next_odm_pipe->stream_res.dsc; in dcn32_update_odm() local
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/linux/include/drm/display/
A Ddrm_dsc_helper.h30 u8 drm_dsc_initial_scale_value(const struct drm_dsc_config *dsc);
31 u32 drm_dsc_flatness_det_thresh(const struct drm_dsc_config *dsc);
/linux/drivers/gpu/drm/amd/display/dc/link/
A Dlink_dpms.c783 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in link_set_dsc_on_stream() local
822 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); in link_set_dsc_on_stream()
823 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); in link_set_dsc_on_stream()
905 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); in link_set_dsc_on_stream()
923 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in link_set_dsc_pps_packet() local
929 if (!dsc) in link_set_dsc_pps_packet()
949 dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]); in link_set_dsc_pps_packet()
987 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in link_set_dsc_enable() local
992 if (!dsc) in link_set_dsc_enable()
1011 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in link_update_dsc_config() local
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/
A Ddcn20_resource.c1064 struct dcn20_dsc *dsc = in dcn20_dsc_create() local
1067 if (!dsc) { in dcn20_dsc_create()
1073 return &dsc->base; in dcn20_dsc_create()
1079 *dsc = NULL; in dcn20_dsc_destroy()
1335 *dsc = NULL; in dcn20_acquire_dsc()
1339 *dsc = pool->dscs[pipe_idx]; in dcn20_acquire_dsc()
1346 *dsc = dsc_old; in dcn20_acquire_dsc()
1354 *dsc = pool->dscs[i]; in dcn20_acquire_dsc()
1367 if (pool->dscs[i] == *dsc) { in dcn20_release_dsc()
1369 *dsc = NULL; in dcn20_release_dsc()
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